Register Description by Block
Table 13: ADC Registers (Sheet 2 of 2)
Register Name
ANA_ADC_BIAS
Addr Mode Bits
0053 R/W
[5]
Rst
01
[4:3]
[2:1]
[0]
ANA_ADC_RED_0 0054 R/W
[7:0]
7F
ANA_ADC_RED_1 0055 R/W
[7]
0F
[5:0]
ANA_ADC_RED_2 0056 R/W
[6:4]
00
[3:2]
[1]
[0]
ANA_ADC_GRN_0
ANA_ADC_GRN_1
0057
0058
See ANA_ADC_RED_0.
See ANA_ADC_RED_1.
ANA_ADC_GRN_2 0059 See ANA_ADC_RED_2.
ANA_ADC_BLU_0 005A See ANA_ADC_RED_0.
ANA_ADC_BLU_1
ANA_ADC_BLU_2
005B
005C
See ANA_ADC_RED_1.
See ANA_ADC_RED_2.
a. Normal value for ANA_FS216_CTRL is 0Ah.
b. When xclk = 27MHz
Description
ADC Band gap power control
0*: on
1: off
IREF adjustment for internal bias,
when ADCBIAS[2:1]=01 (or 11)
00*: 600uA
01: 750uA
10: 300uA
11: 450uA
Must be set to 01
ADC power control
0: on
1*: off
GAIN CONTROL
2.74mV/step
00: 0.35V
FF: 1.05V
VREF
0*: internal
1: external
OFFSET CONTROL: 2.9mV/step
Channel Skew control
LSB = 200ps(typ)
Amp bandwidth adjust
00*: BW=250MHz (min)
01: BW=150MHz (min)
10: reserved
11: BW=40MHz (min)
Clamp Control
0*: enabled
1: disabled
ADC Dithering (ADTH block)
0*: disabled
1: enabled
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ADE3800