ADE3800SXL View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ADE3800SXL

Analog LCD Display Engine for XGA and SXGA Resolutions with Embedded LVDS and RSDS Transmitters

STMicroelectronics 

Register Description by Block

ADE3800

Register Name

ADTH_MAT_CTRL

ADTH_FRAME_CTRL

ADTH_CLAMP_CTRL

ADTH_TEST_DITHER

Table 14: ADTH Registers

Addr Mode Bits Rst

Description

03D0 R/W

03D1 R/W

03D2 R/W

03D3 R/W

[7:6] 01

[5:4]

[3]

[2]

[1]

[0]

[7:4] 00

[3:0]

[7:4] 00

[3:0]

[2:0] 00

amplitude_offset

adth_out[2:0] = (dither_amplitude + amplitude_offset)

%8

dither_amplitude

0*: dither amplitude range: 0-7

1: dither amplitude range: 0-6

2: dither amplitude range: 0-5

3: dither amplitude range: 0-4

1: vertical start position of dither matrix changes by

FRAME_OFFSET

1: horizontal start position of dither matrix changes by

FRAME_OFFSET

Clamp polarity. To be set to 1.

0: adth_out[2:0] = 3

1*: AFE dither amplitude enabled

frame_offset

Offset the start position of the dither matrix from frame

to frame by frame_offset.

See frame_len.

frame_len

Reset dither matrix start position after frame_len +1

number of frames when frame_len > 0.

See frame_offset.

clamp_begin

Delay and mute the clamp pulse by 0-15 clock cycles

Note: adth_out[2:0] = 3 during clamping/muting

clamp_end

Mute after the end of clamp pulse for 0-15 clock cycles

Note: adth_out[2:0] = 3 during clamping/muting

For AFE dither amplitude (voltage) calibration.

During vertical blanking

adth_out[2:0] = test_dither

4.5 Line Lock PLL (LLK)

The LLK generates the ADC input pixel sampling clock from an incoming HSync source and a

multiplying factor (MFACTOR, aka Clock). The loop filter parameters and skew (aka Phase) can be

tuned. The phase can be adjusted in steps of 72ps. The minimum LLK generated clock frequency is

13.5 MHz.

The PLL filter has two states with independent filter parameters: Fast and Slow. If while in the Fast

state the phase detector error count remains below a programmable threshold (LLK_LOCK_TOL) for a

programmable number of input lines (LLK_LOCK_LINE_NB), the PLL changes to the Slow state. While

in this state, the Slow filter coefficients apply. In the event that phase detector errors should exceed

LLK_LOCK_TOL for one or more lines, the PLL returns to the Fast state in one line, and Fast filter

coefficients again apply.

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