ADE3800
Register Description by Block
Register Name
OMUX_CTRL3
OMUX_CTRL4
OMUX_CTRL5
OMUX_CTRL6
Table 33: OMUX Registers (Sheet 2 of 3)
Addr Mode Bits Rst
Description
0C33 R/W
[7]
00 0*: select RSDS even bits first
(normal)
1: select RSDS odd bits first
R/W
[4]
1: RSDS split buffer enable
R/W
[1]
0*: 128 pin mapping
1: 100 pin mapping
R/W
[0]
1: RSDS outputs active (see Table 34)
0C34 R/W
[7]
00 1: invert RSDS data pair 4
R/W
[6]
1: invert RSDS data pair 5
R/W
[5]
1: invert RSDS data pair 6
R/W
[4]
R/W
[3]
R/W
[2]
1: invert RSDS data pair 7
1: invert RSDS data pair 16
1: invert RSDS data pair 17
LVDS
Debug
Pattern
R/W
[1]
R/W
[0]
1: invert RSDS data pair 18
1: invert RSDS data pair 20
RSDS
Debug
Pattern
0C35 R/W
[7]
00 1: invert RSDS data pair 11
R/W
[6]
1: invert RSDS data pair 10
R/W
[5]
1: invert RSDS data pair 9
R/W
[4]
1: invert RSDS data pair 8
R/W
[3]
1: invert RSDS data pair 0
R/W
[2]
1: invert RSDS data pair 1
R/W
[1]
1: invert RSDS data pair 2
R/W
[0]
1: invert RSDS data pair 3
0C36 R/W
[7]
00 1: invert RSDS data pair 19
R/W
[6]
1: invert RSDS data pair 22
R/W
[5]
1: invert RSDS data pair 23
R/W
[4]
1: invert RSDS data pair 25
R/W
[3]
1: invert RSDS data pair 24
R/W
[2]
1: invert RSDS data pair 15
R/W
[1]
1: invert RSDS data pair 14
R/W
[0]
1: invert RSDS data pair 13
95/138