ADE3800
Register Description by Block
The split line buffer can delay and re-interleave the input pixel stream so that a 2 ppc output can
drive both the first and the half line pixels simultaneously. This is commonly used for TCON
applications where the column drivers are split into two groups (left and right halves of the screen)
and driven at ½ the pixel rate. Control signals need to be similarly delayed in the TCON to account
for the ½ line temporal shift. Latency is not important as long as the timing relationship between
HSync, vsync, enable and data is preserved at the output.
Figure 20: Mux block diagram
8
rin[7:0]
8
gin[7:0]
8
bin[7:0]
8
right
shift
8
right
shift
8
right
shift
8
byte
red &
flip
blue
swap
8
byte
flip
single to F
24
double wide L
converter O
48
P
& RSDS S
data pair
hc lk
iinversion
8
byte
flip
LVDS data
swap &
inversion
RSDS
data pair
function
24
56
enab_in
hsync_in
vsync_in
14
tcon_in[7:0]
pwm_a_in 2
pw m _b_in
dotclk
dotclkx2 (otclk)
tci[13:0]
FLOPS
8
56
24
6
tcon_out lvds_out rsds_out
[7:0]
[55:0] [23:0]
lvd s_ c lk _ o ut
rs d s_ c lk a _ o u t
rs d s_ c lk b _ o u t
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