ADE7816ACPZ-RL View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
ADE7816ACPZ-RL Datasheet PDF : 48 Pages
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Data Sheet
ADE7816
REGISTER MAPS
Table 12. Calibration and Power Quality Registers
Register
Address Name
Bit
Bit Length During
R/W1 Length Communication2
0x4380 VGAIN
R/W 24
32 ZPSE
0x4381 IAGAIN
R/W 24
32 ZPSE
0x4382 IBGAIN
R/W 24
32 ZPSE
0x4383 ICGAIN
R/W 24
32 ZPSE
0x4384 IDGAIN
R/W 24
32 ZPSE
0x4385 IEGAIN
R/W 24
32 ZPSE
0x4386 IFGAIN
R/W 24
32 ZPSE
0x4387 Reserved
R/W 24
32 ZPSE
0x4388 DICOEFF
R/W 24
32 ZPSE
Type 3
S
S
S
S
S
S
S
S
S
0x4389 HPFDIS
R/W 24
32 ZPSE
S
0x438A VRMSOS
R/W 24
32 ZPSE
S
0x438B IARMSOS
R/W 24
32 ZPSE
S
0x438C IBRMSOS
R/W 24
32 ZPSE
S
0x438D ICRMSOS
R/W 24
32 ZPSE
S
0x438E IDRMSOS
R/W 24
32 ZPSE
S
0x438F IERMSOS
R/W 24
32 ZPSE
S
0x4390 IFRMSOS
R/W 24
32 ZPSE
S
0x4391 AWGAIN
R/W 24
32 ZPSE
S
0x4392 AWATTOS
R/W 24
32 ZPSE
S
0x4393 BWGAIN
R/W 24
32 ZPSE
S
0x4394 BWATTOS
R/W 24
32 ZPSE
S
0x4395 CWGAIN
R/W 24
32 ZPSE
S
0x4396 CWATTOS
R/W 24
32 ZPSE
S
0x4397 DWGAIN
R/W 24
32 ZPSE
S
0x4398 DWATTOS
R/W 24
32 ZPSE
S
0x4399 EWGAIN
R/W 24
32 ZPSE
S
0x439A EWATTOS
R/W 24
32 ZPSE
S
0x439B FWGAIN
R/W 24
32 ZPSE
S
0x439C FWATTOS
R/W 24
32 ZPSE
S
0x439D AVARGAIN
R/W 24
32 ZPSE
S
0x439E AVAROS
R/W 24
32 ZPSE
S
0x439F BVARGAIN
R/W 24
32 ZPSE
S
0x43A0 BVAROS
R/W 24
32 ZPSE
S
0x43A1 CVARGAIN
R/W 24
32 ZPSE
S
0x43A2 CVAROS
R/W 24
32 ZPSE
S
0x43A3 DVARGAIN
R/W 24
32 ZPSE
S
0x43A4 DVAROS
R/W 24
32 ZPSE
S
0x43A5 EVARGAIN
R/W 24
32 ZPSE
S
0x43A6 EVAROS
R/W 24
32 ZPSE
S
0x43A7 FVARGAIN
R/W 24
32 ZPSE
S
0x43A8 FVAROS
R/W 24
32 ZPSE
S
0x43A9 Reserved
0x43AA Reserved
0x43AB WTHR1
R/W 24
32 ZP
U
0x43AC WTHR0
R/W 24
32 ZP
U
Default
Value
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
Description
Voltage gain adjustment.
Current Channel A current gain adjustment.
Current Channel B current gain adjustment.
Current Channel C current gain adjustment.
Current Channel D current gain adjustment.
Current Channel E current gain adjustment.
Current Channel F current gain adjustment.
This register should be ignored.
Register used in the digital integrator algorithm.
When the integrator is enabled, this register
should be set to 0xFFF8000.
Disables the high-pass filter for all channels.
Voltage rms offset.
Current Channel A current rms offset.
Current Channel B current rms offset.
Current Channel C current rms offset.
Current Channel D current rms offset.
Current Channel E current rms offset.
Current Channel F current rms offset.
Channel A active power gain adjust.
Channel A active power offset adjust.
Channel B active power gain adjust.
Channel B active power offset adjust.
Channel C active power gain adjust.
Channel C active power offset adjust.
Channel D active power gain adjust
Channel D active power offset adjust.
Channel E active power gain adjust.
Channel E active power offset adjust.
Channel F active power gain adjust.
Channel F active power offset adjust.
Channel A reactive power gain adjust.
Channel A reactive power offset adjust.
Channel B reactive power gain adjust.
Channel B reactive power offset adjust.
Channel C reactive power gain adjust.
Channel C reactive power offset adjust.
Channel D reactive power gain adjust.
Channel D reactive power offset adjust.
Channel E reactive power gain adjust.
Channel E reactive power offset adjust.
Channel F reactive power gain adjust.
Channel F reactive power offset adjust.
This register should be ignored.
This register should be ignored.
Most significant 24 bits of the WTHR[47:0]
threshold.
Least significant 24 bits of the WTHR[47:0]
threshold.
Rev. 0 | Page 37 of 48
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