ADE7816ACPZ-RL View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
ADE7816ACPZ-RL Datasheet PDF : 48 Pages
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ADE7816
Data Sheet
Address
0xE607
0xE608
0xE609 to
0xE60B
0xE60C
0xE60D
0xE60E
0xE60F
0xE610 to
0xE616
0xE617
0xE618
0xE700
0xE701
0xE702
0xE703
0xE704
0xE705
0xE706
0xE707
0xE7E3
0xE7FE
0xEBFF
Register
Name
Period
CHNOLOAD
Reserved
R/W1
R
R
Bit
Length
16
16
Bit Length During
Communication2
16
16
Type3
U
U
Default
Value4
N/A
N/A
LINECYC
R/W 16
16
ZXTOUT
R/W 16
16
COMPMODE R/W 16
16
Gain
R/W 16
16
Reserved
U
0xFFFF
U
0xFFFF
U
0x01FF
U
0x0000
CHSIGN
R
16
16
CONFIG
R/W 16
16
MMODE
R/W 8
8
ACCMODE R/W 8
8
LCYCMODE R/W 8
8
PEAKCYC
R/W 8
8
SAGCYC
R/W 8
8
Reserved
HSDC_CFG R/W 8
8
Version
R/W 8
8
Reserved
R/W 8
8
U
N/A
U
0x0000
U
0x1C
U
0x00
U
0x78
U
0x00
U
0x00
U
0x00
U
U
0x00
Reserved
Reserved
8
8
0xEC00
Reserved
0xEC01
CONFIG2
R/W 8
8
U
0x00
Description
Line period.
Channel no load register.
For proper operation, do not write to
these addresses.
Line cycle accumulation mode count.
Zero-crossing timeout count.
Computation mode register.
PGA gains at ADC inputs (see Table 22).
This register should be ignored.
Power sign register.
Configuration register.
Measurement mode register.
Accumulation mode register.
Line accumulation mode.
Peak detection half line cycles.
Sag detection half line cycles.
This register should be ignored.
HSDC configuration register.
Version of die.
Register protection (see the Register
Protection section).
Register protection key (see the Register
Protection section).
This address can be used in manipulating
the SSE/HSA pin when SPI is chosen as
A
A
the active port (see the Communication
section for details).
This register should be ignored.
Configuration register (see Table 29).
1 R is read, and W is write.
2 32 ZP is a 24- or 20-bit, signed or unsigned register that is transmitted as a 32-bit word with 8 or 12 MSBs, respectively, padded with 0s. 32 SE is a 24-bit, signed register
that is transmitted as a 32-bit word that is sign extended to 32 bits.
3 U indicates an unsigned register, and S indicates a signed register in twos complement format.
4 N/A is not applicable.
REGISTER DESCRIPTIONS
Table 16. HPFDIS Register (Address 0x4389)
Bits
Default Value
Description
[23:0]
0x000000
When HPFDIS = 0x000000, all high-pass filters in voltage and current channels are enabled.
When the register is set to any nonzero value, all high-pass filters are disabled.
Table 17. IPEAK Register (Address 0xE500)
Bits
Bit Name
Default Value
[31:27]
Reserved
0x00000
26
IPCHANNEL2
0x0
25
IPCHANNEL1
0x0
24
IPCHANNEL0
0x0
[23:0]
IPEAKVAL[23:0]
0x0
Description
These bits should be ignored.
The C or F current channel generated the IPEAKVAL[23:0] value.
The B or E current channel generated the IPEAKVAL[23:0] value.
The A or D current channel generated the IPEAKVAL[23:0] value.
Current channel peak value
Table 18. VPEAK Register (Address 0xE501)
Bits
Bit Name
Default Value
[31:24]
Reserved
0x00000
[23:0]
VPEAKVAL[23:0]
0x0
Description
These bits should be ignored.
Voltage channel peak value.
Rev. 0 | Page 40 of 48
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