ADP3193AJCPZ-RL View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
ADP3193AJCPZ-RL Datasheet PDF : 32 Pages
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ADP3193A
MASTER CLOCK FREQUENCY
The clock frequency of the ADP3193A is set with an external
resistor connected from the RT pin to ground. The frequency
follows the graph in Figure 3. To determine the frequency per
phase, the clock is divided by the number of phases in use. If all
phases are in use, divide by 3. If PWM3 is tied to VCC, divide
the master clock by 2 for the frequency of the remaining phases.
OUTPUT VOLTAGE DIFFERENTIAL SENSING
The ADP3193A includes differential sensing, high accuracy
VID DAC and reference, and a low offset error amplifier. This
maintains a worst-case specification of ±7.7 mV differential
sensing error over its full operating output voltage and temperature
range. The output voltage is sensed between the FB pin and the
FBRTN pin. FB should be connected through a resistor to the
regulation point, usually the remote sensing pin of the micro-
processor. FBRTN should be connected directly to the remote
sensing ground point. The internal VID DAC and precision
reference are referenced to FBRTN, which has a minimal current
of 65 μA to allow accurate remote sensing. The internal error
amplifier compares the output of the DAC to the FB pin to
regulate the output voltage.
OUTPUT CURRENT SENSING
The ADP3193A provides a dedicated current sense amplifier
(CSA) to monitor the total output current for proper voltage
positioning vs. load current and for current-limit detection.
Sensing the load current at the output gives the total average
current being delivered to the load, which is an inherently more
accurate method than peak current detection or sampling the
current across a sensing element, such as the low-side MOSFET.
Depending on the objectives of the system, this amplifier can be
configured in several ways:
• Output inductor DCR sensing without a thermistor for
lowest cost.
• Output inductor DCR sensing with a thermistor for
improved accuracy in tracking inductor temperature.
• Sensing resistor for highest accuracy measurements.
The positive input of the CSA is connected to the CSREF pin,
which is connected to the output voltage. The inputs to the
amplifier are summed together through resistors from the sensing
element, such as the switch node side of the output inductors,
to the inverting input CSSUM. The feedback resistor between
CSCOMP and CSSUM sets the gain of the amplifier, and a filter
capacitor is placed in parallel with this resistor. The gain of the
amplifier is programmable by adjusting the feedback resistor.
The difference between CSREF and CSCOMP is also used as a
differential input for the current-limit comparator.
To provide the best accuracy for sensing current, the CSA has a
low offset input voltage and the sensing gain is set by the external
resistor.
CURRENT CONTROL MODE AND
THERMAL BALANCE
The ADP3193A has individual inputs (SW1 to SW3) for each
phase that are used to monitor the current. This information is
combined with an internal ramp to create a current-balancing
feedback system that has been optimized for initial current balance
accuracy and dynamic thermal balancing during operation. This
current balance information is independent of the average output
current information used for positioning, as described in the
Output Current Sensing section.
The magnitude of the internal ramp can be set to optimize the
transient response of the system. It also monitors the supply voltage
for feedforward control for changes in the supply. A resistor
connected from the power input voltage to the RAMPADJ pin
determines the slope of the internal PWM ramp. External resistors
can be placed in series with individual phases to create an inten-
tional current imbalance, such as when one phase has better
cooling and can support higher currents. Resistors RSW1 through
RSW3 (see Figure 10) can be used for adjusting thermal balance
in this 3-phase example. It is best to have the ability to add these
resistors during the initial design; therefore, ensure that place-
holders are provided in the layout.
To increase the current in any given phase, enlarge RSW for that
phase (make RSW = 0 for the hottest phase, and do not change it
during balancing). Increasing RSW to only 500 Ω results in a
substantial increase in phase current. Increase each RSW value
by small amounts to achieve balance, starting with the coolest
phase first.
VOLTAGE CONTROL MODE
A high gain, high bandwidth voltage mode error amplifier is used
for the voltage mode control loop. The control input voltage to
the positive input is set via the VID logic according to the voltages
listed in Table 4.
This voltage is also offset by the droop voltage for active
positioning of the output voltage as a function of current,
commonly known as active voltage positioning. The output
of the amplifier is the COMP pin, which sets the termination
voltage for the internal PWM ramps.
The negative input (FB) is tied to the output sense location with
Resistor RBB and is used for sensing and controlling the output
voltage at this point. A current source (equal to IREF) from the
FB pin flowing through RBB is used for setting the no load offset
voltage from the VID voltage. The no load voltage is negative with
respect to the VID DAC. The main loop compensation is incor-
porated into the feedback network between FB and COMP pins.
Rev. 0 | Page 10 of 32
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