ADP3193AJCPZ-RL View Datasheet(PDF) - Analog Devices
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Description
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ADP3193AJCPZ-RL Datasheet PDF : 32 Pages
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THEORY OF OPERATION
The ADP3193A combines a multimode, fixed-frequency PWM
control with multiphase logic outputs for use in 2- and 3-phase
synchronous buck CPU core supply power converters. The internal
VID DAC is designed to interface with the Intel 8-bit VRD/VRM 11
and 7-bit VRD/VRM 10.x CPUs. Multiphase operation is impor-
tant for producing the high currents and low voltages demanded by
today’s microprocessors. Handling the high currents in a single-
phase converter increases thermal demands on the components
in the system, such as the inductors and MOSFETs.
The multimode control of the ADP3193A ensures a stable,
high performance topology for the following:
• Balancing currents and thermals between phases
• High speed response at the lowest possible switching
frequency and output decoupling
• Minimizing thermal switching losses by using lower
frequency operation
• Tight load line regulation and accuracy
• High current output due to 3-phase operation
• Reduced output ripple due to multiphase cancellation
• PC board layout noise immunity
• Ease of use and design due to independent component
selection
• Flexibility in design by allowing optimization for either low
cost or high performance
START-UP SEQUENCE
The ADP3193A follows the VR11 start-up sequence shown in
Figure 7. After both the EN and UVLO conditions are met,
the DELAY pin goes through one cycle (TD1). The first three
clock cycles of TD2 are blanked from the PWM outputs and
used for phase detection, as explained in the Phase Detection
Sequence section. Then, the soft start ramp is enabled (TD2),
and the output increases to the boot voltage of 1.1 V. The boot
hold time is determined by the DELAY pin as it goes through a
second cycle (TD3). During TD3, the processor VID pins settle
to the required VID code. When TD3 is over, the ADP3193A
soft starts either up or down to the final VID voltage (TD4).
After TD4 has been completed and the PWRGD masking time
(equal to VID on-the-fly masking) is completed, a third ramp
on the DELAY pin sets the PWRGD blanking (TD5).
ADP3193A
5V
SUPPLY
UVLO
THRESHOLD
VTT I/O
(ADP3193A EN)
DELAY
0.85V
VDELAY(TH)
(1.7V)
SS
VCC_CORE
VR READY
(ADP3193A PWRGD)
CPU
VID INPUTS
VBOOT
1V
(1.1V)
TD3
TD1
VBOOT
(1.1V)
TD2
VVID
VVID
TD4
TD5
50µs
VID INVALID
VID VALID
Figure 7. System Start-Up Sequence
PHASE DETECTION SEQUENCE
During startup, the number of operational phases and their
phase relationship is determined by the internal circuitry that
monitors the PWM outputs. Normally, the ADP3193A operates
as a 3-phase PWM controller. Connecting the PWM3 pin to
VCC programs 2-phase operation.
Prior to soft start, while EN is low, the PWM3 pin sinks approxi-
mately 100 μA. An internal comparator checks the voltage on
PWM3 and compares it with a threshold of 3 V. If the pin is tied
to VCC, it is above the threshold. Otherwise, an internal current
sink pulls the pin to GND, which is below the threshold. PWM1
and PWM2 are low during the phase detection interval that occurs
during the first three clock cycles of TD2. After this time, if PWM3
is not pulled to VCC, the 100 μA current sink is removed, and it
functions as normal PWM output. If PWM3 is pulled to VCC,
the 100 μA current source is removed, and it is put into a high
impedance state.
The PWM outputs are logic-level devices intended for driving
external gate drivers such as the ADP3120A. Because each phase
is monitored independently, operation approaching 100% duty
cycle is possible. In addition, more than one output can be on at
the same time to allow overlapping phases.
Rev. 0 | Page 9 of 32
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