ADP3193AJCPZ-RL View Datasheet(PDF) - Analog Devices
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Description
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ADP3193AJCPZ-RL Datasheet PDF : 32 Pages
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ADP3193A
CURRENT REFERENCE
The IREF pin is used to set an internal current reference. This
reference current sets IFB, IDELAY, ISS, and ILIMIT. A resistor to
ground programs the current based on the 1.5 V output.
1.5 V
IREF =
R IREF
Typically, RIREF is set to 100 kΩ to program IREF = 15 μA.
Therefore,
IFB = IREF = 15 μA
IDELAY = IREF = 15 μA
ISS = IREF = 15 μA
ILIMIT = 2/3 (IREF) = 10 μA
FAST ENHANCED PWM MODE
Fast enhanced PWM mode is intended to improve the transient
response of the ADP3193A to a load step-up. In previous genera-
tions of controllers, when a load step-up occurred, the controller
could only respond to the load change after the PWM signal
was turned on. Enhanced PWM mode allows the controller to
immediately respond when a load step-up occurs. This allows the
phases to respond more quickly when a load increase takes place.
DELAY TIMER
The delay times for the start-up timing sequence are set with
a capacitor from the DELAY pin to ground. In UVLO or when
EN is logic low, the DELAY pin is held at ground. After the
UVLO and EN signals are asserted, the first delay time (TD1 in
Figure 7) is initiated. A current flows out of the DELAY pin to
charge CDLY. This current is equal to IREF, which is normally
15 μA. A comparator monitors the DELAY voltage with a
threshold of 1.7 V. The delay time is therefore set by the IREF
current charging a capacitor from 0 V to 1.7 V. This DELAY pin
is used for multiple delay timings (TD1, TD3, and TD5) during
the start-up sequence. In addition, DELAY is used for timing
the current-limit latch-off, as explained in the Current-Limit,
Short-Circuit, and Latch-Off Protection section.
SOFT START
The soft start times for the output voltage are set with a capacitor
from the SS pin to ground. After TD1 and the phase detection
cycle have been completed, the SS time (TD2 in Figure 7) starts.
The SS pin is disconnected from GND, and the capacitor is charged
up to the 1.1 V boot voltage by the SS amplifier, which has an
output current equal to IREF (normally 15 μA). The voltage at
the FB pin follows the ramping voltage on the SS pin, limiting
the inrush current during startup. The soft start time depends
on the value of the boot voltage and CSS.
When the SS voltage is within 100 mV of the boot voltage, the
boot voltage delay time (TD3 in Figure 7) starts. The end of the
boot voltage delay time signals the beginning of the second soft
start time (TD4 in Figure 7). The SS voltage changes from the
boot voltage to the programmed VID DAC voltage (either higher
or lower) using the SS amplifier with the output current equal to
IREF. The voltage of the FB pin follows the ramping voltage of
the SS pin, limiting the inrush current during the transition from
the boot voltage to the final DAC voltage. The second soft start
time depends on the boot voltage, the programmed VID DAC
voltage, and the CSS.
If EN is taken low or if VCC drops below UVLO, DELAY and
SS are reset to ground to be ready for another soft start cycle.
Figure 8 shows typical start-up waveforms for the ADP3193A.
1
2
3
4
CH1 1V
CH3 1V
CH2 1V
CH4 10V
M 1ms
T 40.4%
A CH1 700mV
Figure 8. Typical Start-Up Waveforms
(Channel 1: CSREF, Channel 2: DELAY,
Channel 3: SS, Channel 4: Phase 1 Switch Node)
CURRENT-LIMIT, SHORT-CIRCUIT, AND
LATCH-OFF PROTECTION
The ADP3193A compares a programmable current-limit
setpoint to the voltage from the output of the current sense
amplifier. The level of current limit is set with the resistor from
the ILIMIT pin to ground. During operation, the current from
ILIMIT is equal to 2/3 of IREF, resulting in 10 μA normally. This
current through the external resistor sets the ILIMIT voltage,
which is internally scaled to provide a current limit threshold of
82.6 mV/V. If the difference in voltage between CSREF and
CSCOMP rises above the current-limit threshold, the internal
current-limit amplifier controls the internal COMP voltage to
maintain the average output current at the limit.
If the limit is reached and TD5 in Figure 7 has completed, a
latch-off delay time starts, and the controller shuts down if the
fault is not removed. The current-limit delay time shares the
DELAY pin timing capacitor with the start-up sequence timing.
However, during current limit, the DELAY pin current is reduced
to IREF/4. A comparator monitors the DELAY voltage and shuts
off the controller when the voltage reaches 1.7 V. Therefore,
Rev. 0 | Page 11 of 32
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