ADP3193AJCPZ-RL View Datasheet(PDF) - Analog Devices
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Description
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ADP3193AJCPZ-RL Datasheet PDF : 32 Pages
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APPLICATION INFORMATION
The design parameters for a typical Intel VRD 11 compliant
CPU application are as follows:
• Input voltage (VIN) = 12 V
• VID setting voltage (VVID) = 1.400 V
• Duty cycle (D) = 0.117
• Nominal output voltage at no load (VONL) = 1.381 V
• Nominal output voltage at 65 A load (VOFL) = 1.316 V
• Static output voltage drop based on a 1.0 mΩ load line (RO)
from no load to full load (VD) = VONL − VOFL =
1.381 V − 1.316 V = 65 mV
• Maximum output current (IO) = 65 A
• Maximum output current step (ΔIO) = 50 A
• Maximum output current slew rate (SR) = 200 A/μs
• Number of phases (n) = 3
• Switching frequency per phase (fSW) = 330 kHz
SETTING THE CLOCK FREQUENCY
The ADP3193A uses a fixed-frequency control architecture.
The frequency is set by an external timing resistor (RT). The
clock frequency and the number of phases determine the switching
frequency per phase, which relates directly to switching losses as
well as to the sizes of the inductors, the input capacitors, and the
output capacitors. With n = 3 for three phases, a clock frequency
of 990 kHz sets the switching frequency (fSW) of each phase to
330 kHz, which represents a practical trade-off between the
switching losses and the sizes of the output filter components.
Figure 3 shows that to achieve a 990 kHz oscillator frequency,
the correct value for RT is 169 kΩ (closest 1% resistor is 169 kΩ).
Alternatively, the value for RT can be calculated using
RT
=
n×
1
f SW × 6 pF
(1)
where 6 pF is the internal IC component values. For good initial
accuracy and frequency stability, a 1% resistor is recommended.
SOFT START DELAY TIME
The value of CSS sets the soft start time. The ramp is generated
with a 15 μA internal current source. The value for CSS can be
found using
C SS
=15 μA ×
TD2
V BOOT
(2)
where TD2 is the desired soft start time, and VBOOT is internally
set to 1.1 V.
Assuming a desired TD2 time of 1.4 ms, CSS is 19 nF. The closest
standard value for CSS is 18 nF. Although CSS also controls the time
delay for TD4 (determined by the final VID voltage), the minimum
specification for TD4 is 0 ns. This means that as long as the TD2
time requirement is met, TD4 is within the specification.
ADP3193A
CURRENT-LIMIT LATCH-OFF DELAY TIMES
The start-up and current-limit delay times are determined by
the capacitor connected to the DELAY pin. The first step is to
set CDLY for the TD1, TD3, and TD5 delay times (see Figure 7).
The DELAY ramp (IDELAY) is generated using a 15 μA internal
current source. The value for CDLY can be approximated using
C DLY
= I DELAY
× TD(x)
VDELAY(TH )
(3)
where:
TD(x) is the desired delay time for TD1, TD3, and TD5.
VDELAY(TH) is the DELAY threshold voltage and is given as 1.7 V.
In this example, 2 ms is chosen for all three delay times, which
meets Intel specifications. Solving for CDLY results in a value of
17.6 nF. The closest standard value for CDLY is 18 nF.
When the ADP3193A surpasses the current limit, the internal
current source changes from 15 μA to 3.75 μA. As a result, the
latch-off delay time becomes four times longer than the start-up
delay time. Note that longer latch-off delay times can be achieved
by placing a resistor in parallel with CDLY.
INDUCTOR SELECTION
The choice of inductance for the inductor determines the ripple
current in the inductor. Less inductance leads to more ripple
current, which increases the output ripple voltage and conduction
losses in the MOSFETs. However, using smaller inductors allows
the converter to meet a specified peak-to-peak transient deviation
with less total output capacitance. Conversely, a higher inductance
means lower ripple current and reduced conduction losses, but
more output capacitance is required to meet the same peak-to-
peak transient deviation.
In any multiphase converter, a practical value for the peak-to-
peak inductor ripple current is less than 50% of the maximum
dc current in the same inductor. Equation 4 shows the relationship
between the inductance, oscillator frequency, and peak-to-peak
ripple current in the inductor.
IR
=
VVID × (1 − D)
f SW × L
(4)
Equation 5 can be used to determine the minimum inductance
based on a given output ripple voltage.
L ≥ VVID × RO × (1 − (n × D))
(5)
f SW × VRIPPLE
Rev. 0 | Page 19 of 32
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