ADP3193AJCPZ-RL View Datasheet(PDF) - Analog Devices

Part Name

Description

Manufacturer

ADP3193AJCPZ-RL

8-Bit, Programmable, 2-Phase to 3-Phase, Synchronous Buck Controller

Analog Devices 

ADP3193A

the current-limit latch-off delay time is set by the current of

IREF/4 charging the delay capacitor from 0 V to 1.7 V. This delay

is four times longer than the delay time during the start-up

sequence.

The current-limit delay time starts only after the TD5 is

complete. If there is a current limit during startup, the

ADP3193A goes through TD1 to TD5, and then starts the

latch-off time. Because the controller continues to cycle the

phases during the latch-off delay time, the controller returns to

normal operation and the DELAY capacitor is reset to GND if

the short is removed before the 1.7 V threshold is reached.

The latch-off function can be reset by either removing and

reapplying the supply voltage to the ADP3193A or by briefly

toggling the EN pin low. To disable the short-circuit latch-off

function, an external resistor should be placed in parallel with

CDLY. This prevents the DELAY capacitor from charging up to

the 1.7 V threshold. The addition of this resistor causes a slight

increase in the delay times.

During startup, when the output voltage is below 200 mV,

a secondary current limit is active. This is necessary because

the voltage swing of CSCOMP cannot go below ground. This

secondary current limit controls the internal COMP voltage

to the PWM comparators to 1.5 V. This limits the voltage drop

across the low-side MOSFETs through the current balance

circuitry. An inherent per-phase current limit protects individual

phases if one or more phases stop functioning because of a faulty

component. This limit is based on the maximum normal mode

COMP voltage. Typical overcurrent latch-off waveforms are

shown in Figure 9.

1

2

3

4

CH1 1V

CH3 2V

CH2 1V

CH4 10V

M 2ms

T 61.8%

A CH1 680mV

Figure 9. Overcurrent Latch-Off Waveforms

(Channel 1: CSREF, Channel 2: DELAY,

Channel 3: COMP, Channel 4: Phase 1 Switch Node)

DYNAMIC VID

The ADP3193A can dynamically change the VID inputs while

the controller is running. This allows the output voltage to

change while the supply is running and supplying current to the

load. This is commonly referred to as VID on-the-fly (OTF). A

VID OTF can occur under light or heavy load conditions. The

processor signals the controller by changing the VID inputs in

multiple steps from the start code to the finish code. This

change can be positive or negative.

When a VID input changes state, the ADP3193A detects the

change and ignores the DAC inputs for a minimum of 400 ns.

This time prevents a false code due to logic skew while the eight

VID inputs are changing. Additionally, the first VID change

initiates the PWRGD and crowbar blanking functions for a

minimum of 100 μs to prevent a false PWRGD or crowbar

event. Each VID change resets the internal timer.

POWER-GOOD MONITORING

The power-good comparator monitors the output voltage via

the CSREF pin. The PWRGD pin is an open-drain output whose

high level, when connected to a pull-up resistor, indicates that

the output voltage is within the specified nominal limits, which

are based on the VID voltage setting. PWRGD goes low if the

output voltage is outside of this specified range, if the VID DAC

inputs are in no CPU mode, or if the EN pin is pulled low. PWRGD

is blanked during a VID OTF event for a period of 200 μs to

prevent false signals during the time the output is changing.

The PWRGD circuitry also incorporates an initial turn-on

delay time (TD5) based on the DELAY timer. Prior to the

SS voltage reaching the programmed VID DAC voltage and the

PWRGD masking time finishing, the PWRGD pin is held low.

When the SS pin is within 100 mV of the programmed DAC

voltage, the capacitor on the DELAY pin begins to charge.

A comparator monitors the DELAY voltage and enables

PWRGD when the voltage reaches 1.7 V. The PWRGD delay

time is, therefore, set by a current of IREF charging a capacitor

from 0 V to 1.7 V.

OUTPUT CROWBAR

To protect the load and output components of the supply, the

PWM outputs are driven low, which turns on the low-side

MOSFETs when the output voltage exceeds the upper crowbar

threshold. This crowbar action stops when the output voltage

falls below the release threshold of approximately 300 mV.

Turning on the low-side MOSFETs pulls down the output as

the reverse current builds up in the inductors. If the output

overvoltage is due to a short in the high-side MOSFET, this

action current limits the input supply or blows its fuse,

protecting the microprocessor from being destroyed.

Rev. 0 | Page 12 of 32

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