ADP3193AJCPZ-RL View Datasheet(PDF) - Analog Devices

Part Name

Description

Manufacturer

ADP3193AJCPZ-RL

8-Bit, Programmable, 2-Phase to 3-Phase, Synchronous Buck Controller

Analog Devices 

OUTPUT ENABLE AND UVLO

For the ADP3193A to begin switching, the input supply (VCC)

to the controller must be higher than the UVLO threshold and

the EN pin must be higher than its 0.85 V threshold. This

initiates a system start-up sequence. If either UVLO or EN is

less than its respective threshold, the ADP3193A is disabled.

This holds the PWM outputs at ground, shorts the DELAY

capacitor to ground, and forces PWRGD and OD signals low.

ADP3193A

In the application circuit (see Figure 10), the OD pin should be

connected to the OD inputs of the ADP3120A drivers. Grounding

OD disables the drivers such that both DRVH and DRVL are

grounded. This feature is important in preventing the discharge

of the output capacitors when the controller is shut off. If the

driver outputs are not disabled, a negative voltage can be generated

during output due to the high current discharge of the output

capacitors through the inductors.

Rev. 0 | Page 13 of 32

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