ADS6444IRGCT View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ADS6444IRGCT

QUAD CHANNEL, 14-BIT, 125/105/80/65 MSPS ADC WITH SERIAL LVDS OUTPUTS

STMicroelectronics 

ADS6445, ADS6444

ADS6443, ADS6442

SLAS531 – MAY 2007

www.ti.com

Since some functions are controlled using both the parallel pins and serial registers, the priority between the two

is determined by a priority table (refer to Table 4).

Table 4. Priority Between Parallel Pins and Serial Registers

PIN

FUNCTIONS SUPPORTED

PRIORITY

CFG1 to CFG4

As described in Table 8 to

Table 11

Register bits can control the modes only if the register bit <OVRD> is high. If <OVRD> bit

is low, then the control voltage on these parallel pins determines the function.

PDN

Global Power Down

Register bit <PDN GLOBAL> controls global power down only if PDN pin is low. If PDN is

high, device is in global power down.

SEN

Serial Interface Enable

Coarse gain is controlled by register bit <COARSE GAIN>only if the <OVRD> bit is high.

Else, device has 0 dB coarse gain.

Internal/External Reference setting is determined by register bit <REF>.

SCLK, SDATA

Serial Interface Clock and

Serial Interface Data pins

Register bits <PATTERNS> control the sync and deskew output patterns.

Power down is determined by bit <PDN GLOBAL>

AVDD

3R

(5/8) AVDD

2R

(3/8) AVDD

3R

GND

(5/8) AVDD

GND

AVDD

(3/8) AVDD

To Parallel Pin

Figure 3. Simple Scheme to Configure Parallel Pins

16

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