ADSP-BF514BBCZ-3 View Datasheet(PDF) - Analog Devices

Part Name

Description

Manufacturer

ADSP-BF514BBCZ-3

DSP Microcomputer

Analog Devices 

ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F

TIMING SPECIFICATIONS

Clock and Reset Timing

Table 23 and Figure 7 describe clock and reset operations. Per

the CCLK and SCLK timing specifications in Table 9 , Table 10,

and Table 11 on Page 21, combinations of CLKIN and clock

multipliers must not select core/peripheral clocks in excess of

the processor’s speed grade.

Table 23. Clock and Reset Timing

Parameter

Min

Max

Unit

Timing Requirements

fCKIN

CLKIN Frequency (Commercial/Industrial Models1, 2, 3, 4 12

50

fCKIN

CLKIN Frequency (Automotive Models)1, 2, 3, 4

14

50

tCKINL

CLKIN Low Pulse1

10

tCKINH

CLKIN High Pulse1

10

tWRST

RESET Asserted Pulse Width Low5

11 × tCKIN

Switching Characteristic

MHz

MHz

ns

ns

ns

tBUFDLAY

CLKIN to CLKBUF Delay

11

ns

1 Applies to PLL bypass mode and PLL nonbypass mode.

2 Combinations of the CLKIN frequency and the PLL clock multiplier must not exceed the allowed fVCO, fCCLK, and fSCLK settings discussed in Table 9 through Table 11 on Page 21.

3 The tCKIN period (see Figure 7) equals 1/fCKIN.

4 If the DF bit in the PLL_CTL register is set, the minimum fCKIN specification is 24 MHz for commercial/industrial models and 28 MHz for automotive models.

5 Applies after power-up sequence is complete. See Table 24 and Figure 8 for power-up reset timing.

CLKIN

CLKBUF

tCKIN

tCKINL

tCKINH

RESET

tWRST

tBUFDLAY

tBUFDLAY

Figure 7. Clock and Reset Timing

Table 24. Power-Up Reset Timing

Parameter

Timing Requirements

tRST_IN_PWR RESET Deasserted after the VDDINT, VDDEXT, VDDRTC, VDDMEM, VDDOTP, and CLKIN Pins are

Stable and Within Specification

Min

3500 × tCKIN

Max

Unit

ns

Rev. B | Page 27 of 68 | January 2011

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