AT/TS80C31X2
Reset = Vss after a high pulse
during at least 24 clock cycles
RST
VCC
ICC
VCC
VCC
P0
EA
(NC)
CLOCK
SIGNAL
XTAL2
XTAL1
VSS
Figure 14-2. Operating ICC Test Condition
All other pins are disconnected.
VCC
ICC
VCC
VCC
Reset = Vss after a high pulse
P0
during at least 24 clock cycles
RST EA
(NC)
CLOCK
SIGNAL
XTAL2
XTAL1
VSS
Figure 14-3. ICC Test Condition, Idle Mode
All other pins are disconnected.
Reset = Vss after a high pulse
during at least 24 clock cycles
RST
VCC
ICC
VCC
VCC
P0
EA
(NC)
XTAL2
XTAL1
VSS
All other pins are disconnected.
Figure 14-4. ICC Test Condition, Power-Down Mode
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4428D–8051–08/05