ATMEGA64L-8MI View Datasheet(PDF) - Atmel Corporation

Part Name

Description

Manufacturer

ATMEGA64L-8MI

8-bit AVR® Microcontroller with 64K Bytes In-System Programmable Flash

Atmel Corporation 

Pull-up and Bus Keeper

Timing

ATmega64(L)

before G low (tsu) must not exceed address valid to ALE low (tAVLLC) minus PCB wiring

delay (dependent on the capacitive load).

Figure 12. External SRAM Connected to the AVR

D[7:0]

AD7:0

ALE

AVR

A15:8

RD

WR

DQ

G

A[7:0]

SRAM

A[15:8]

RD

WR

The pull-ups on the AD7:0 ports may be activated if the corresponding Port Register is

written to one. To reduce power consumption in sleep mode, it is recommended to dis-

able the pull-ups by writing the Port Register to zero before entering sleep.

The XMEM interface also provides a Bus Keeper on the AD7:0 lines. The Bus Keeper

can be disabled and enabled in software as described in “External Memory Control Reg-

ister B – XMCRB” on page 32. When enabled, the Bus Keeper will keep the previous

value on the AD7:0 bus while these lines are tri-stated by the XMEM interface.

External memory devices have different timing requirements. To meet these require-

ments, the ATmega64 XMEM interface provides four different wait states as shown in

Table 4. It is important to consider the timing specification of the external memory

device before selecting the wait-state. The most important parameters are the access

time for the external memory compared to the set-up requirement of the ATmega64.

The access time for the external memory is defined to be the time from receiving the

chip select/address until the data of this address actually is driven on the bus. The

access time cannot exceed the time from the ALE pulse is asserted low until data must

be stable during a read sequence (tLLRL+ tRLRH - tDVRH in Table 138 to Table 145 on page

338). The different wait states are set up in software. As an additional feature, it is possi-

ble to divide the external memory space in two sectors with individual wait-state

settings. This makes it possible to connect two different memory devices with different

timing requirements to the same XMEM interface. For XMEM interface timing details,

please refer to Figure 159 to Figure 162, and Table 138 to Table 145.

Note that the XMEM interface is asynchronous and that the waveforms in the following

figures are related to the internal system clock. The skew between the internal and

external clock (XTAL1) is not guaranteed (varies between devices, temperature, and

supply voltage). Consequently the XMEM interface is not suited for synchronous

operation.

27

2490G–AVR–03/04

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