ATMEGA64L-8MI View Datasheet(PDF) - Atmel Corporation

Part Name

Description

Manufacturer

ATMEGA64L-8MI

8-bit AVR® Microcontroller with 64K Bytes In-System Programmable Flash

Atmel Corporation 

XMEM Register

Description

MCU Control Register –

MCUCR

External Memory Control

Register A – XMCRA

Bit

Read/Write

Initial Value

7

6

5

SRE SRW10

SE

R/W

R/W

R/W

0

0

0

4

SM1

R/W

0

3

SM0

R/W

0

2

SM2

R/W

0

1

IVSEL

R/W

0

0

IVCE

R/W

0

MCUCR

• Bit 7 – SRE: External SRAM/XMEM Enable

Writing SRE to one enables the External Memory Interface.The pin functions AD7:0,

A15:8, ALE, WR, and RD are activated as the alternate pin functions. The SRE bit over-

rides any pin direction settings in the respective data direction registers. Writing SRE to

zero, disables the External Memory Interface and the normal pin and data direction set-

tings are used.

• Bit 6 – SRW10: Wait State Select Bit

For a detailed description in non ATmega103 compatibility mode, see common descrip-

tion for the SRWn bits below (XMRA description). In ATmega103 compatibility mode,

writing SRW10 to one enables the wait state and one extra cycle is added during

read/write strobe as shown in Figure 14.

Bit

Read/Write

Initial Value

7

6

5

4

3

2

1

0

–

SRL2

SRL1

SRL0 SRW01 SRW00 SRW11

–

XMCRA

R

R/W

R/W

R/W

R/W

R/W

R/W

R

0

0

0

0

0

0

0

0

• Bit 7 – Res: Reserved Bit

This is a reserved bit and will always read as zero. When writing to this address location,

write this bit to zero for compatibility with future devices.

• Bit 6..4 – SRL2, SRL1, SRL0: Wait State Sector Limit

It is possible to configure different wait states for different external memory addresses.

The external memory address space can be divided in two sectors that have separate

wait-state bits. The SRL2, SRL1, and SRL0 bits select the split of the sectors, see Table

3 and Figure 11. By default, the SRL2, SRL1, and SRL0 bits are set to zero and the

entire external memory address space is treated as one sector. When the entire SRAM

address space is configured as one sector, the wait states are configured by the SRW11

and SRW10 bits.

30 ATmega64(L)

2490G–AVR–03/04

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