Figure 13. External Data Memory Cycles without Wait State(1)
(SRWn1 = 0 and SRWn0 =0)
T1
T2
T3
T4
System Clock (CLKCPU)
ALE
A15:8 Prev. Addr.
Address
DA7:0 Prev. Data
Address XX
Data
WR
DA7:0 (XMBK = 0) Prev. Data
Address
Data
DA7:0 (XMBK = 1) Prev. Data
Address
Data
RD
Note:
1. SRWn1 = SRW11 (upper sector) or SRW01 (lower sector), SRWn0 = SRW10 (upper
sector) or SRW00 (lower sector).
The ALE pulse in period T4 is only present if the next instruction accesses the RAM
(internal or external).
Figure 14. External Data Memory Cycles with SRWn1 = 0 and SRWn0 = 1(1)
T1
T2
T3
T4
T5
System Clock (CLKCPU)
ALE
A15:8 Prev. Addr.
Address
DA7:0 Prev. Data
Address XX
Data
WR
DA7:0 (XMBK = 0) Prev. Data
Address
Data
DA7:0 (XMBK = 1) Prev. Data
Address
Data
RD
Note:
1. SRWn1 = SRW11 (upper sector) or SRW01 (lower sector), SRWn0 = SRW10 (upper
sector) or SRW00 (lower sector).
The ALE pulse in period T5 is only present if the next instruction accesses the RAM
(internal or external).
28 ATmega64(L)
2490G–AVR–03/04