AVR_RESET (0xC)
ATmega64(L)
Figure 149. State Machine Sequence for Changing the Instruction Word
1
Test-Logic-Reset
0
0
Run-Test/Idle 1
Select-DR Scan 1
Select-IR Scan 1
0
1 Capture-DR
0
1 Capture-IR
0
0
Shift-DR
0
Shift-IR
0
1
Exit1-DR
1
1
Exit1-IR
1
0
0
Pause-DR
0
Pause-IR
0
1
0
Exit2-DR
1
0
Exit2-IR
1
1
Update-DR
1
0
Update-IR
1
0
The AVR specific public JTAG instruction for setting the AVR device in the Reset mode
or taking the device out from the Reset mode. The TAP controller is not reset by this
instruction. The one bit Reset Register is selected as Data Register. Note that the reset
will be active as long as there is a logic 'one' in the Reset Chain. The output from this
chain is not latched.
The active states are:
• Shift-DR: The Reset Register is shifted by the TCK input.
2490G–AVR–03/04
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