ATmega64(L)
0x001E
jmp
TIM0_COMP ; Timer0 Compare Handler
0x0020
jmp
TIM0_OVF
; Timer0 Overflow Handler
0x0022
jmp
SPI_STC
; SPI Transfer Complete Handler
0x0024
jmp
USART0_RXC ; USART0 RX Complete Handler
0x0026
jmp
USART0_DRE ; USART0,UDR Empty Handler
0x0028
jmp
USART0_TXC ; USART0 TX Complete Handler
0x002A
jmp
ADC
; ADC Conversion Complete Handler
0x002C
jmp
EE_RDY
; EEPROM Ready Handler
0x002E
jmp
ANA_COMP
; Analog Comparator Handler
0x0030
jmp
TIM1_COMPC ; Timer1 CompareC Handler
0x0032
jmp
TIM3_CAPT ; Timer3 Capture Handler
0x0034
jmp
TIM3_COMPA ; Timer3 CompareA Handler
0x0036
jmp
TIM3_COMPB ; Timer3 CompareB Handler
0x0038
jmp
TIM3_COMPC ; Timer3 CompareC Handler
0x003A
jmp
TIM3_OVF
; Timer3 Overflow Handler
0x003C
jmp
USART1_RXC ; USART1 RX Complete Handler
0x003E
jmp
USART1_DRE ; USART1,UDR Empty Handler
0x0040
jmp
USART1_TXC ; USART1 TX Complete Handler
0x0042
jmp
TWI
; Two-wire Serial Interface Handler
0x0044
jmp
SPM_RDY
; SPM Ready Handler
;
0x0046 RESET: ldi
r16, high(RAMEND); Main program start
0x0047
out
SPH,r16
; Set Stack Pointer to top of RAM
0x0048
ldi
r16, low(RAMEND)
0x0049
0x004A
out
SPL,r16
sei
; Enable interrupts
0x004B
<instr> xxx
... ... ... ...
When the BOOTRST Fuse is unprogrammed, the Boot section size set to 8K bytes and
the IVSEL bit in the MCUCR Register is set before any interrupts are enabled, the most
typical and general program setup for the Reset and Interrupt Vector Addresses is:
Address Labels Code
Comments
0x0000 RESET: ldi
r16,high(RAMEND); Main program start
0x0001
out
SPH,r16
; Set Stack Pointer to top of RAM
0x0002
ldi
r16,low(RAMEND)
0x0003
0x0004
out
SPL,r16
sei
; Enable interrupts
0x0005
<instr> xxx
;
.org 0x7002
0x7002
jmp
EXT_INT0 ; IRQ0 Handler
0x7004
jmp
EXT_INT1 ; IRQ1 Handler
...
...
...
;
0x7044
jmp
SPM_RDY ; Store Program Memory Ready Handler
61
2490G–AVR–03/04