ATXMEGA64A1-CU View Datasheet(PDF) - Atmel Corporation

Part Name

Description

Manufacturer

ATXMEGA64A1-CU

8/16-bit XMEGA A1 Microcontroller

Atmel Corporation 

XMEGA A1

28. PDI - Program and Debug Interface

28.1 Features

28.2 Overview

• PDI - Program and Debug Interface (Atmel proprietary 2-pin interface)

• JTAG Interface (IEEE std. 1149.1 compliant)

• Boundary-scan capabilities according to the IEEE Std. 1149.1 (JTAG)

• Access to the OCD system

• Programming of Flash, EEPROM, Fuses and Lock Bits

The programming and debug facilities are accessed through the JTAG and PDI physical inter-

faces. The PDI physical interface uses one dedicated pin together with the Reset pin, and no

general purpose pins are used. JTAG uses four general purpose pins on PORTB.

The PDI is an Atmel proprietary protocol for communication between the microcontroller and

Atmel’s or third party development tools.

28.3 IEEE 1149.1 (JTAG) Boundary-scan

28.3.1

28.3.2

The JTAG physical layer handles the basic low-level serial communication over four I/O lines

named TMS, TCK, TDI, and TDO. It complies to the IEEE Std. 1149.1 for test access port and

boundary scan.

Boundary-scan Order

Table 29-12 on page 55 shows the Scan order between TDI and TDO when the Boundary-scan

chain is selected as data path. Bit 0 is the LSB; the first bit scanned in, and the first bit scanned

out. The scan order follows the pin-out order. Bit 4, 5, 6 and 7 of Port B is not in the scan chain,

since these pins constitute the TAP pins when the JTAG is enabled.

Boundary-scan Description Language Files

Boundary-scan Description Language (BSDL) files describe Boundary-scan capable devices in

a standard format used by automated test-generation software. The order and function of bits in

the Boundary-scan Data Register are included in this description. BSDL files are available for

ATxmega384/256/192/128/64A1 devices.

See Table 29-12 on page 55 for ATxmega384/256/192/128/64A1 Boundary Scan Order.

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8067L–AVR–08/10

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