ATXMEGA64A1-CU View Datasheet(PDF) - Atmel Corporation

Part Name

Description

Manufacturer

ATXMEGA64A1-CU

8/16-bit XMEGA A1 Microcontroller

Atmel Corporation 

8067L–AVR–08/10

XMEGA A1

8. Setting HIRES PR bit makes PWM output unavailable

Setting the HIRES Power Reduction (PR) bit for PORTx will make any Frequency or PWM

output for the corresponding Timer/Counters (TCx0 and TCx1) unavailable on the pin even if

the Hi-Res is not used.

Problem fix/Workaround

Do not write the HIRES PR bit on PORTx when frequency or PWM output from TCx0/1 is

used.

9. BOD will be enabled after any reset

If any reset source goes active, the BOD will be enabled and keep the device in reset if the

VCC voltage is below the programmed BOD level. During Power-On Reset, reset will not be

released until VCC is above the programmed BOD level even if the BOD is disabled.

Problem fix/Workaround

Do not set the BOD level higher than VCC even if the BOD is not used.

10. Propagation delay analog Comparator increasing to 2 ms at -40 °C

When the analog comparator is used at temperatures reaching down to -40 °C, the propaga-

tion delay will increase to ~2 ms.

Problem fix/Workaround

None

11. Sampled BOD in Active mode will cause noise when bandgap is used as reference

Using the BOD in sampled mode when the device is running in Active or Idle mode will add

noise on the bandgap reference for ADC and DAC.

Problem fix/Workaround

If the bandgap is used as reference for either the ADC or the DAC, the BOD must not be set

in sampled mode.

12. Default setting for SDRAM refresh period too low

If the SDRAM refresh period is set to a value less then 0x20, the SDRAM content may be

corrupted when accessing through On-Chip Debug sessions.

Problem fix/Workaround

The SDRAM refresh period (REFRESHH/L) should not be set to a value less then 0x20.

13. Flash Power Reduction Mode can not be enabled when entering sleep mode

If Flash Power Reduction Mode is enabled when entering Power-save or Extended Standby

sleep mode, the device will only wake up on every fourth wake-up request.

If Flash Power Reduction Mode is enabled when entering Idle sleep mode, the wake-up time

will vary with up to 16 CPU clock cycles.

Problem fix/Workaround

Disable Flash Power Reduction mode before entering sleep mode.

14. JTAG enable does not override Analog Comparator B output

When JTAG is enabled this will not override the Anlog Comparator B (ACB)ouput, AC0OUT

on pin 7 if this is enabled.

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