C8051F045 View Datasheet(PDF) - Silicon Laboratories

Part Name

Description

Manufacturer

C8051F045

Mixed Signal ISP Flash MCU Family

Silicon Laboratories 

C8051F040/1/2/3/4/5/6/7

We will adjust the length of the 4 bit segments so that their sum is as close as possible to the desired bit

time. Since each segment must be an integer multiple of the time quantum (tq), the closest achievable bit

time is 22 tq (994.642 ns), yielding a bit rate of 1.00539 Mbit/sec. The Sync_Seg is a constant 1 tq. The

Prop_Seg must be greater than or equal to the propagation delay of 400 ns; we choose 9 tq (406.899 ns).

The remaining time quanta (tq) in the bit time are divided between Phase_Seg1 and Phase_Seg2 as

shown in Figure 18.1. We select Phase_Seg1 = 6 tq and Phase_Seg2 = 6 tq.

Phase_Seg1 + Phase_Seg2 = Bit Time – Sync_Seg + Prop_Seg

Note 1: If Phase_Seg1 + Phase_Seg2 is even, then Phase_Seg2 = Phase_Seg1.

Note 2: Phase_Seg2 should be at least 2 tq.

Equation 18.1. Assigning the Phase Segments

The Synchronization Jump Width (SJW) timing parameter is defined by Figure 18.2. It is used for determin-

ing the value written to the Bit Timing Register and for determining the required oscillator tolerance. Since

we are using a quartz crystal as the system clock source, an oscillator tolerance calculation is not needed.

SJW = min ( 4, Phase_Seg1 )

Equation 18.2. Synchronization Jump Width (SJW)

The value written to the Bit Timing Register can be calculated using Equation 18.3. The BRP Extension

register is left at its reset value of 0x0000.

BRPE = BRP - 1 = BRP Extension Register = 0x0000

SJWp = SJW - 1 = min ( 4, 6 ) – 1 = 3

TSEG1 = (Prop_Seg + Phase_Seg1 - 1) = 9 + 6 - 1 = 14

TSEG2 = (Phase_Seg2 - 1) = 5

Bit Timing Register = (TSEG2 * 0x1000) + (TSEG1 * 0x0100) + (SJWp * 0x0040) + BRPE = 0x5EC0

Equation 18.3. Calculating the Bit Timing Register Value

The following steps are performed to initialize the CAN timing registers:

Step 1. Set the SFRPAGE register to CAN0_PAGE.

Step 2. Set the INIT the CCE bits to ‘1’ in the CAN Control Register accessible through the

CAN0CN SFR.

Step 3. Set the CAN0ADR to 0x03 to point to the Bit Timing Register.

230

Rev. 1.5

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