C8051F066 View Datasheet(PDF) - Silicon Laboratories

Part Name

Description

Manufacturer

C8051F066

Mixed Signal ISP Flash MCU Family

Silicon Laboratories 

C8051F060/1/2/3/4/5/6/7

5.4. Calibration

The ADCs are calibrated for linearity, offset, and gain in production. ADC0 and ADC1 can also be indepen-

dently calibrated for each of these parameters in-system. Calibrations are initiated using bits in the ADC0

or ADC1 Configuration Register. The calibration coefficients can be accessed using the ADC Calibration

Pointer Register (ADC0CPT, Figure 5.22) and the ADC Calibration Coefficient Register (ADC0CCF,

Figure 5.23). The CPTR bits in ADC0CPT allow the ADC0CCF register to read and write specific calibra-

tion coefficients. Figure 5.19 shows the Calibration Coefficient locations.

Figure 5.19. Calibration Coefficient Locations

ADC0CPT

Bits 5-0

0x00

.

.

0x12

0x13

0x14

0x15

0x16

Bit7

Offset7

Gain7

ADC0CCF

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Linearity Calibration Coefficients (locations 0x00 through 0x12)

Offset6

Gain6

Offset5

Offset13

Gain5

Offset4

Offset12

Gain4

Gain12

Offset3

Offset11

Gain3

Gain11

Offset2

Offset10

Gain2

Gain10

Offset1

Offset9

Gain1

Gain9

Bit0

Offset0

Offset8

Gain0

Gain8

The ADCs are calibrated for linearity in production. Under normal circumstances, no additional linearity

calibration is necessary. If linearity calibrations are desired, they can be initiated by setting the ADCnLCAL

bit to ‘1’. When the calibration is finished, the ADCnLCAL bit will be set to ‘0’ by the hardware. Linearity

Calibration Coefficients are stored in the locations shown in Figure 5.19.

Offset and gain calibrations can be performed using either internal or external voltages as calibration

sources. The ADCnSCAL bit determines whether the internal or external voltages are used in the calibra-

tion process. To ensure accuracy, offset calibration should be done prior to a gain calibration. The offset

and gain calibration coefficients are decoded in Figure 5.20. Offset calibration is initiated by setting the

ADCnOCAL bit to ‘1’. When the calibration is finished, the ADCnOCAL bit will be set to ‘0’ by the hardware.

Offset calibration can compensate for offset errors of approximately ±3.125% of full scale. The offset value

is added to the AINnG input prior to digitization by the ADC. Gain calibration is initiated by setting the ADC-

nGCAL bit to ‘1’. When the calibration is finished, the ADCnGCAL bit will be set to ‘0’ by the hardware.

Gain calibration can compensate for slope errors of approximately ±3.125%. The gain value is added to

the ADC’s VREF path to change the slope of the converter’s transfer function. Figure 5.21 shows how the

offset and gain values affect the analog signals used by the ADC.

66

Rev. 1.2

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