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C8051F911-GM View Datasheet(PDF) - Silicon Laboratories

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Description
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C8051F911-GM Datasheet PDF : 318 Pages
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C8051F91x-C8051F90x
9. Memory Organization
The memory organization of the CIP-51 System Controller is similar to that of a standard 8051. There are
two separate memory spaces: program memory and data memory. Program and data memory share the
same address space but are accessed via different instruction types. The memory organization of the
C8051F91x-C8051F90x device family is shown in Figure 9.1
PROGRAM/DATA MEMORY
(FLASH)
0x01FF
0x0000
0x3FFF
0x3C00
0x3BFF
C8051F912/11
Scrachpad Memory
(DATA only)
RESERVED
16KB FLASH
0x0000
(In-System
Programmable in 512
Byte Sectors)
0x01FF
0x0000
0x1FFF
C8051F902/1
Scrachpad Memory
(DATA only)
8KB FLASH
(In-System
Programmable in 512
Byte Sectors)
0x0000
DATA MEMORY
(RAM)
INTERNAL DATA ADDRESS SPACE
Upper 128 RAM
Special Function
Registers
(Indirect Addressing Only) (Direct Addressing Only)
0
F
(Direct and Indirect
Addressing)
Bit Addressable
General Purpose
Registers
Lower 128 RAM
(Direct and Indirect
Addressing)
EXTERNAL DATA ADDRESS SPACE
C8051F912/11/02/01
0x1FFF
Unpopulated Address Space
0x0200
0x01FF
0x0000
XRAM - 512 Bytes
(accessable using MOVX
instruction)
Note: Code compatible devices with up to 64 kB Flash and 4 kB RAM are available as the C8051F93x-92x family.
Figure 9.1. C8051F91x-C8051F90x Memory Map
Rev. 1.0
107

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