C8051F911-GM View Datasheet(PDF) - Silicon Laboratories

Part Name

Description

Manufacturer

C8051F911-GM

Single/Dual Battery, 0.9–3.6 V, 16–8 kB, SmaRTClock, 12/10-Bit ADC MCU

Silicon Laboratories 

C8051F91x-C8051F90x

9.1. Program Memory

The CIP-51 core has a 64 kB program memory space. The C8051F91x-C8051F90x devices implement

16 kB (C8051F912/1) or 8 kB (C8051F902/1) of this program memory space as in-system, re-

programmable Flash memory, organized in a contiguous block from addresses 0x0000 to 0x3BFF

(C8051F912/1) or 0x1FFF (C8051F902/1). The last byte of this contiguous block of addresses serves as

the security lock byte for the device. Any addresses above the lock byte are reserved.

C8051F912/1

C8051F902/1

(SFLE=1)

Scratchpad

(Data Only)

0x01FF

0x0000

C8051F912/1

(SFLE=0)

Reserved Area

Lock Byte

Lock Byte Page

0xFFFF

0x3C00

0x3BFF

0x3BFE

0x3A00

0x39FF

Flash Memory Space

C8051F902/1

(SFLE=0)

Unpopulated

Address Space

(Reserved)

Lock Byte

Lock Byte Page

Flash Memory Space

0x0000

Figure 9.2. Flash Program Memory Map

0xFFFF

0x8000

0x1FFF

0x1FFE

0x1E00

0x1BFF

0x0000

9.1.1. MOVX Instruction and Program Memory

The MOVX instruction in an 8051 device is typically used to access external data memory. On the

C8051F91x-C8051F90x devices, the MOVX instruction is normally used to read and write on-chip XRAM,

but can be re-configured to write and erase on-chip Flash memory space. MOVC instructions are always

used to read Flash memory, while MOVX write instructions are used to erase and write Flash. This Flash

access feature provides a mechanism for the C8051F91x-C8051F90x to update program code and use

the program memory space for non-volatile data storage. Refer to Section “13. Flash Memory” on

page 132 for further details.

9.2. Data Memory

The C8051F91x-C8051F90x device family include 768 bytes of RAM data memory. 256 bytes of this

memory is mapped into the internal RAM space of the 8051. The remainder of this memory is on-chip

“external” memory. The data memory map is shown in Figure 9.1 for reference.

9.2.1. Internal RAM

There are 256 bytes of internal RAM mapped into the data memory space from 0x00 through 0xFF. The

lower 128 bytes of data memory are used for general purpose registers and scratch pad memory. Either

direct or indirect addressing may be used to access the lower 128 bytes of data memory. Locations 0x00

through 0x1F are addressable as four banks of general purpose registers, each bank consisting of eight

byte-wide registers. The next 16 bytes, locations 0x20 through 0x2F, may either be addressed as bytes or

as 128 bit locations accessible with the direct addressing mode.

The upper 128 bytes of data memory are accessible only by indirect addressing. This region occupies the

same address space as the Special Function Registers (SFR) but is physically separate from the SFR

space. The addressing mode used by an instruction when accessing locations above 0x7F determines

108

Rev. 1.0

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