CS495303(2008) View Datasheet(PDF) - Cirrus Logic

Part Name

Description

Manufacturer

CS495303
(Rev.:2008)

32-bit Audio Decoder DSP Family with Dual DSP Engine Technology

Cirrus Logic 

CS4953xx Data Sheet

32-bit Audio Decoder DSP Family

5.16 Switching Characteristics — UART

UART_CLK period1

UART_CLK duty cycle

Parameter

Symbol Min

tuclki

266

-

40

Setup time for UART_RXD

Hold time for UART_RXD

Delay from CLK transition to TXD transition

tuckrxsu

5

tuckrxdv

5

tucktxdv

-

ttxen

?

ttxhz

?

1. The minimum clock period is limited to DCLKP/32 or the minimum value, whichever is larger.

Max

-

60

-

-

29

?

?

Unit

ns

%

ns

ns

ns

ns

UART_CLK

Y UART_TXD

R UART_RXD

A UART_TX_EN

tucktxdv

ttxen

ttxhz

tuckrxsu

tuckrxdv

PRELIMIN Figure 11. UART Timing

22

Copyright 2008 Cirrus Logic

DS705PP3

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