CS495303(2008) View Datasheet(PDF) - Cirrus Logic
Part Name
Description
Manufacturer
CS495303 Datasheet PDF : 34 Pages
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CS4953xx Data Sheet
32-bit Audio Decoder DSP Family
5.18 Switching Characteristics — DSD Slave Input Port
Parameter
Symbol
DSD_SCLK Pulse Width Low
DSD_SCLK Pulse Width High
DSD_SCLK Frequency
(64x Oversampled)
tsclkl
tsclkh
-
DSD_A / _B valid to DSD_SCLK rising setup time
DSD_SCLK rising to DSD_A or DSD_B hold time
DSD clock to data transition (Phase Modulation mode)
tsdlrs
tsdh
tdpm
Min
78
78
1.024
20
20
-20
Typ Max
-
-
-
-
-
3.2
-
-
-
-
-
20
Unit
ns
ns
MHz
ns
ns
ns
RY Figure 13. Direct Stream Digital - Serial Audio Input Timing
INA 5.19 Switching Characteristics — Digital Audio Output Port
Parameter
DAO_MCLK period1
DAO_MCLK duty cycle1
IM DAO_SCLK period for Master or Slave mode2
DAO_SCLK duty cycle for Master or Slave mode2
Master Mode (Output A1 Mode)2,3
Symbol
Tdaomclk
-
Tdaosclk
-
Min
40
40
40
40
Max
-
60
-
60
Unit
ns
%
ns
%
L DAO_SCLK delay from DAO_MCLK rising edge, DAO_MCLK as an
tdaomsck
-
input
DAO_LRCLK delay from DAO_SCLK transition, respectively4
E DAO_DATA[3:0] delay from DAO_SCLK transition4
Slave Mode (Output A0 Mode)5
tdaomstlr
-
tdaomdv
-
R DAO_DATA[3..0] delay from DAO_SCLK transition4
tdaosdv
19
ns
8
ns
10
ns
15
ns
1. CS4953xx has two Digital Audio Output modules having similar signal names ending in 1 and 2. Both DAO ports
Pshare a common MCLK but have independent SCLKs and LRCLKs.
2. Master mode timing specifications are characterized, not production tested.
3. Master mode is defined as the CS4953xx driving both DAO_SCLK, DAO_LRCLK. When MCLK is an input, it is
divided to produce DAO_SCLK, DAO_LRCLK.
4. This timing parameter is defined from the non-active edge of DAO_SCLK. The active edge of DAO_SCLK is the
point at which the data is valid.
5.Slave mode is defined as DAO_SCLK, DAO_LRCLK driven by an external source.
24
Copyright 2008 Cirrus Logic
DS705PP3
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