CS4953xx Data Sheet
32-bit Audio Decoder DSP Family
Tdaomclk
DAO_MCLK
tdaomsck
DAO_SCLK
tdaomdv , tdaosdv
DAO_DATAn
DAO_LRCLK
tdaomstlr
tdaomstlr
Y Figure 14. Digital Audio Port Timing, MCLK Master Mode
AR 5.20 Switching Characteristics — SDRAM Interface
Refer to Figure 15 through Figure 18.
IN (SD_CLKOUT = SD_CLKIN)
Parameter
SD_CLKIN high time
IM SD_CLKIN low time
SD_CLKOUT rise/fall time
SD_CLKOUT Frequency
SD_CLKOUT duty cycle
L SD_CLKOUT rising edge to signal valid
Signal hold from SD_CLKOUT rising edge
E SD_CLKOUT rising edge to SD_DQMn valid
SD_DQMn hold from SD_CLKOUT rising edge
SD_DATA valid setup to SD_CLKIN rising edge
R SD_DATA valid hold to SD_CLKIN rising edge
PSD_CLKOUT rising edge to ADDRn valid
Symbol
tsdclkh
tsdclkl
tsdclkrf
-
tsdcmdv
tsdcmdh
tsddqv
tsddqh
tsddsu
tsddh
tsdav
Min
2.3
2.3
-
45
-
-
1.38
1.3
1.38
-
Typical
150
1.1
3.8
3.8
Max
-
-
1
55
3.8
-
-
-
-
-
-
Unit
ns
ns
ns
MHz
%
ns
ns
ns
ns
ns
ns
ns
DS705PP3
Copyright 2008 Cirrus Logic
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