CS5101A View Datasheet(PDF) - Cirrus Logic

Part Name

Description

Manufacturer

CS5101A

16-bit, 100 kSps / 20 kSps A/D Converters

Cirrus Logic 

CS5101A CS5102A

2. OVERVIEW

The CS5101A and CS5102A are 2-channel, 16-bit

A/D converters. The devices include an inherent

sample/hold and an on-chip analog switch for 2-

channel operation. Both channels can thus be

sampled and converted at rates up to 50 kSps

each (CS5101A) or 10 kSps each (CS5102A). Al-

ternatively, each of the devices can be operated as

a single channel ADC operating at 100 kSps

(CS5101A) or 20 kSps (CS5102A).

Both the CS5101A and CS5102A can be config-

ured to accept either unipolar or bipolar input rang-

es, and data is output serially in either binary or 2's

complement coding. The devices can be config-

ured in 3 different output modes, as well as an in-

ternal, synchronous loopback mode. The

CS5101A and CS5102A provide coarse

charge/fine charge control, to allow accurate track-

ing of high-slew signals.

3. THEORY OF OPERATION

The CS5101A and CS5102A implement the suc-

cessive approximation algorithm using a charge

redistribution architecture. Instead of the traditional

resistor network, the DAC is an array of binary-

weighted capacitors. All capacitors in the array

share a common node at the comparator's input.

As shown in Figure 3, their other terminals are ca-

pable of being connected to AGND, VREF, or AIN

(1 or 2). When the device is not calibrating or con-

verting, all capacitors are tied to AIN. Switch S1 is

closed and the charge on the array, tracks the in-

put signal.

When the conversion command is issued, switch

S1 opens. This traps the charge on the comparator

side of the capacitor array and creates a floating

node at the comparator's input. The conversion al-

gorithm operates on this fixed charge, and the sig-

nal at the analog input pin is ignored. In effect, the

entire DAC capacitor array serves as analog mem-

ory during conversion much like the hold capacitor

in a sample/hold amplifier.

The conversion consists of manipulating the free

plates of the capacitor array to VREF and AGND to

form a capacitive divider. Since the charge at the

floating node remains fixed, the voltage at that

point depends on the proportion of capacitance

tied to VREF versus AGND. The successive ap-

proximation algorithm is used to find the proportion

of capacitance, which when connected to the refer-

ence will drive the voltage at the floating node to

zero. That binary fraction of capacitance repre-

sents the converter's digital output.

AIN

+

-

VREF

+

-

AGND

+

-

Fine

Coarse

Fine

C

C /2

C /4

C /3 2 ,7 6 8

C /3 2 ,7 6 8

S1

C o a rs e

Fine

Bit 15

MSB

Bit 14

Bit 13

-

Bit 0

Dummy

+

LSB

Ctot = C + C/2 + C/4 + C/8 + ... C/32,768

C o a rs e

Figure 3. Coarse Charge Input Buffers & Charge Redistribution DAC

DS45F6

15

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