CS5101A View Datasheet(PDF) - Cirrus Logic

Part Name

Description

Manufacturer

CS5101A

16-bit, 100 kSps / 20 kSps A/D Converters

Cirrus Logic 

CS5101A CS5102A

4. FUNCTIONAL DESCRIPTION

Monolithic design and inherent sampling architec-

ture make the CS5101A and CS5102A extremely

easy to use.

4.1 Initiating Conversions

A falling transition on the HOLD pin places the in-

put in the hold mode and initiates a conversion cy-

cle. The charge is trapped on the capacitor array

the instant HOLD goes low. The device will com-

plete conversion of the sample within 66 master

clock cycles, then automatically return to the track

mode. After allowing a short time for acquisition,

the device will be ready for another conversion.

In contrast to systems with separate track-and-

holds and A/D converters, a sampling clock can

simply be connected to the HOLD input. The duty

cycle of this clock is not critical. The HOLD input is

latched internally by the master clock, so it need

only remain low for 1/fclk + 20 ns, but no longer

than the minimum conversion time minus two mas-

ter clocks or an additional conversion cycle will be

initiated with inadequate time for acquisition. In

Free Run mode, SCKMOD = OUTMOD = 0, the

device will convert at a rate of CLKIN/80, and the

HOLD input is ignored.

As with any high-resolution A-to-D system, it is rec-

ommended that sampling is synchronized to the

master system clock in order to minimize the ef-

fects of clock feed through. However, the

CS5101A and CS5102A may be operated entirely

asynchronous to the master clock if necessary.

4.2 Tracking the Input

Upon completing a conversion cycle the CS5101A

and CS5102A immediately return to the track

mode. The CH1/2 pin directly controls the input

switch, and therefore directly determines which

channel will be tracked. Ideally, the CH1/2 pin

should be switched during the conversion cycle,

thereby nullifying the input mux switching time, and

guaranteeing a stable input at the start of acquisi-

tion. If, however, the CH1/2 control is changed dur-

ing the acquisition phase, adequate coarse charge

and fine charge time must be allowed before initi-

ating conversion.

When the CS5101A or the CS5102A enters track-

ing mode, it uses an internal input buffer amplifier

to provide the bulk of the charge on the capacitor

array (coarse-charge), thereby reducing the cur-

rent load on the external analog circuitry. Coarse-

charge is internally initiated for 6 clock cycles at the

end of every conversion. The buffer amplifier is

then bypassed, and the capacitor array is directly

connected to the input. This is referred to as fine-

charge, during which the charge on the array is al-

lowed to accurately settle to the input voltage (see

Figure 12).

With a full-scale input step, the coarse-charge in-

put buffer of the CS5101A will charge the capacitor

array within 1% in 650 ns. The converter timing al-

lows 6 clock cycles for coarse charge settling time.

When the CS5101A switches to fine-charge mode,

its slew rate is somewhat reduced. In fine-charge,

the CS5101A can slew at 2 V/µs in unipolar mode.

In bipolar mode, only half the capacitor array is

connected to the analog input, so the CS5101A

can slew at 4V/µs.

With a full-scale input step, the coarse-charge in-

put buffer of the CS5102A will charge the capacitor

array within 1% in 3.75 µs. The converter timing al-

lows 6 clock cycles for coarse charge settling time.

When in fine-charge mode, the CS5102A can slew

at 0.4 V/µs in unipolar mode; and at 0.8 V/µs in bi-

polar mode.

Acquisition of fast slewing signals can be hastened

if the voltage change occurs during or immediately

following the conversion cycle. For instance, in

multiple channel applications (using either the de-

vice's internal channel selector or an external

MUX), channel selection should occur while the

CS5101A or the CS5102A is converting. Multiplex-

er switching and settling time is thereby removed

from the overall throughput equation.

If the input signal changes drastically during the

acquisition period (such as changing the signal

source), the device should be in coarse-charge for

an adequate period following the change. The

CS5101A and CS5102A can be forced into coarse-

charge by bringing CRS/FIN high. The buffer am-

plifier is engaged when CRS/FIN is high, and may

be switched in any number of times during track-

ing. If CRS/FIN is held low, the CS5101A and

CS5102A will only coarse-charge for the first 6

clock cycles following a conversion, and will stay in

DS45F6

17

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