CS5101A View Datasheet(PDF) - Cirrus Logic
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CS5101A Datasheet PDF : 39 Pages
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CS5101A CS5102A
4.5 Analog Input Range/Coding Format
The reference voltage directly defines the input
voltage range in both the unipolar and bipolar con-
figurations. In the unipolar configuration
(BP/UP low), the first code transition occurs
0.5 LSB above AGND, and the final code transition
occurs 1.5 LSBs below VREF. In the bipolar con-
figuration (BP/UP high), the first code transition oc-
curs 0.5 LSB above -VREF and the last transition
occurs 1.5 LSBs below +VREF. The CS5101A and
CS5102A can output data in either 2's comple-
ment, or binary format. If the CODE pin is high, the
output is in 2's complement format with a range of
-32,768 to +32,767. If the CODE pin is low, the out-
put is in binary format with a range of 0 to +65,535.
See Table 1 for output coding.
Table 1. Output Coding
Unipolar Input Voltage
>(VREF-1.5 LSB)
VREF-1.5 LSB
(VREF/2)-0.5 LSB
+0.5 LSB
<(+0.5 LSB)
Offset
Binary
FFFF
FFFF
FFFE
8000
7FFF
0001
0000
0000
Two’s
Complement
7FFF
7FFF
7FFE
0000
FFFF
8001
8000
8000
Bipolar Input Voltage
>(VREF-1.5 LSB)
VREF-1.5 LSB
-0.5 LSB
-VREF+0.5 LSB
<(-VREF+0.5 LSB)
4.6 Output Mode Control
The CS5101A and CS5102A can be configured in
three different output modes, as well as an internal,
synchronous loop-back mode. This allows great
flexibility for design into a wide variety of systems.
The operating mode is selected by setting the
states of the SCKMOD and OUTMOD pins. In all
modes, data is output on SDATA, starting with the
MSB. Each subsequent data bit is updated on the
falling edge of SCLK.
Table 2. Output Mode Control
MODE
PDT
RBT
SSC
FRN
SCKMOD
1
1
0
0
OUTMOD
1
0
1
0
SCLK
Input
Input
Output
Output
CH1/2
Input
Input
Input
Output
HOLD
Input
Input
Input
X
When SCKMOD is high, SCLK is an input, allowing
the data to be clocked out with an external serial
clock at rates up to 5 MHz. Additional clock edges
after #16 will clock out logic 1s on SDATA. Tying
SCKMOD low reconfigures SCLK as an output,
and the converter clocks out each bit as it is deter-
mined during the conversion process, at a rate of
1/4 the master clock speed. Table 2 shows an
overview of the different states of SCKMOD and
OUTMOD, and the corresponding output modes.
4.6.1 Pipelined Data Transmission
PDT mode is selected by tying both SCKMOD and
OUTMOD high. In PDT mode, the SCLK pin is an
input. Data is registered during conversion, and
output during the following conversion cycle.
HOLD must be brought low, initiating another con-
version, before data from the previous conversion
is available on SDATA. If all the data has not been
clocked out before the next falling edge of HOLD,
the old data will be lost (Figure 5).
DS45F6
19
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