CS5509(1995) View Datasheet(PDF) - Cirrus Logic
Part Name
Description
Manufacturer
CS5509 Datasheet PDF : 30 Pages
| |||
CS5509
+1
+1/2
0
-1/2
-1
0
32,768
Codes
Figure 4. CS5509 Differential Nonlinearity plot.
65,535
Analog Input Impedance Considerations
The analog input of the CS5509 can be modeled
as illustrated in Figure 5. Capacitors (15 pF
each) are used to dynamically sample each of
the inputs (AIN+ and AIN-). Every half XIN cy-
cle the switch alternately connects the capacitor
to the output of the buffer and then directly to
the AIN pin. Whenever the sample capacitor is
switched from the output of the buffer to the
AIN pin, a small packet of charge (a dynamic
demand of current) is required from the input
source to settle the voltage of the sample capaci-
tor to its final value. The voltage on the output
of the buffer may differ up to 100 mV from the
actual input voltage due to the offset voltage of
the buffer. Timing allows one half of a XIN
clock cycle for the voltage on the sample capaci-
tor to settle to its final value.
AIN+
Vos
≤ 100
mV
+
-
AIN-
Vos
≤ 100
mV
+
-
15 pF
Internal
Bias
Voltage
15 pF
An equation for the maximum acceptable source
resistance is derived.
Rsmax
=
2XIN
(15pF
+
CEXT)
−1
ln
Ve
+
Ve
15pF(100mv)
(15pF
+
CEXT
This equation assumes that the offset voltage of
the buffer is 100 mV, which is the worst case.
The value of Ve is the maximum error voltage
which is acceptable. CEXT is the combination
of any external or stray capacitance.
For a maximum error voltage (Ve) of 10 µV in
the CS5509 (1/4LSB at 16-bits), the above equa-
tion indicates that when operating from a
32.768 kHz XIN, source resistances up to
110 kΩ are acceptable in the absence of external
capacitance (CEXT = 0).
The VREF+ and VREF- inputs have nearly the
same structure as the AIN+ and AIN- inputs.
Therefore, the discussion on analog input imped-
ance applies to the voltage reference inputs as
well.
Figure 5. Analog Input Model
DS125F1
13
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