CS5509(1995) View Datasheet(PDF) - Cirrus Logic

Part Name

Description

Manufacturer

CS5509
(Rev.:1995)

Single Supply, 16-Bit A/D Converter

Cirrus Logic 

Reading Serial Data

SDATA is the output pin for the serial data.

When CS goes low after new data becomes

available (DRDY goes low), the SDATA pin

comes out of Hi-Z with the MSB data bit pre-

sent. SCLK is the input pin for the serial clock.

If the MSB data bit is on the SDATA pin, the

first rising edge of SCLK enables the shifting

mechanism. This allows the falling edges of

SCLK to shift subsequent data bits out of the

port. Note that if the MSB data bit is output and

the SCLK signal is high, the first falling edge of

SCLK will be ignored because the shifting

mechanism has not become activated. After the

first rising edge of SCLK, each subsequent fall-

ing edge will shift out the serial data. Once the

LSB is present, the falling edge of SCLK will

cause the SDATA output to go to Hi-Z and

DRDY to return high. The serial port register

will be updated with a new data word upon the

completion of another conversion if the serial

port has been emptied, or if the CS is inactive

(high).

CS can be operated asynchronously to the

DRDY signal. The DRDY signal need not be

monitored as long as the CS signal is taken low

for at least two XIN clock cycles plus 200 ns

prior to SCLK being toggled. This ensures that

CS has gained control over the serial port.

Power Supplies and Grounding

The analog and digital supply pins to the

CS5509 are brought out on separate pins to

minimize noise coupling between the analog and

digital sections of the chip. In the digital section

of the chip the supply current flows into the

VD+ pin and out of the GND pin. As a CMOS

device, the CS5509 requires that the supply volt-

age on the VA+ pin always be more positive

than the voltage on any other pin of the device.

If this requirement is not met, the device can

latch-up or be damaged. In all circumstances the

VA+ voltage must remain more positive than the

16

CS5509

VD+ or GND pins; VD+ must remain more

positive than the GND pin.

Figure 9a illustrates the System Connection Dia-

gram for the CS5509. Note that all supply pins

are bypassed with 0.1 µF capacitors and that the

VD+ digital supply is derived from the VA+

supply. Figure 9b illustrates the CS5509 operat-

ing from a +5V analog supply and +3.3V digital

supply.

When using separate supplies for VA+ and

VD+, VA+ must be established first. VD+

should never become more positive than VA+

under any operating condition. Remember to in-

vestigate transient power-up conditions, when

one power supply may have a faster rise time.

Schematic & Layout Review Service

Confirm Optimum

Schematic & Layout

Before Building Your Board.

For Our Free Review Service

Call Applications Engineering.

Call: (512) 445-7222

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