CS5509(1995) View Datasheet(PDF) - Cirrus Logic
Part Name
Description
Manufacturer
CS5509 Datasheet PDF : 30 Pages
| |||
PIN DESCRIPTIONS*
CHIP SELECT
CS 1
CONVERT CONV 2
CALIBRATE CAL 3
CRYSTAL IN
XIN 4
CRYSTAL OUT XOUT 5
BIPOLAR/UNIPOLAR BP/UP 6
DIFFERENTIAL ANALOG INPUT AIN+ 7
DIFFERENTIAL ANALOG INPUT AIN- 8
*Pinout applies to both PDIP and SOIC
CS5509
16 DRDY DATA READY
15 SDATA SERIAL DATA OUTPUT
14 SCLK SERIAL CLOCK INPUT
13 VD+
POSITIVE DIGITAL POWER
12 GND
GROUND
11 VA+
POSITIVE ANALOG POWER
10 VREF- VOLTAGE REFERENCE INPUT
9 VREF+ VOLTAGE REFERENCE INPUT
Clock Generator
XIN; XOUT - Crystal In; Crystal Out, Pins 4, 5.
A gate inside the chip is connected to these pins and can be used with a crystal to provide the
master clock for the device. Alternatively, an external (CMOS compatible) clock can be
supplied into the XIN pin to provide the master clock for the device. Loss of clock will put the
device into a lower powered state (approximately 70% power reduction).
Serial Output I/O
CS - Chip Select, Pin 1.
This input allows an external device to access the serial port.
DRDY - Data Ready, Pin 16.
Data Ready goes low at the end of a digital filter convolution cycle to indicate that a new
output word has been placed into the serial port. DRDY will return high after all data bits are
shifted out of the serial port or two master clock cycles before new data becomes available if
the CS pin is inactive (high).
SDATA - Serial Data Output, Pin 15.
SDATA is the output pin of the serial output port. Data from this pin will be output at a rate
determined by SCLK. Data is output MSB first and advances to the next data bit on the falling
edges of SCLK. SDATA will be in a high impedance state when not transmitting data.
SCLK - Serial Clock Input, Pin 14.
A clock signal on this pin determines the output rate of the data from the SDATA pin. This pin
must not be allowed to float.
DS125F1
19
Share Link: 