CS8900A-CQZ View Datasheet(PDF) - Cirrus Logic

Part Name

Description

Manufacturer

CS8900A-CQZ

Crystal LAN™ Ethernet Controller

Cirrus Logic 

CS8900A

Crystal LAN™ Ethernet Controller

the LineCTL register (Register 13) and is de-

scribed in Table 31.

Register 13, LineCTL

Bit Bit Name

Operation

7 SerTxON When set, transmission enabled.

8

AUIonly When set, AUI selected (takes

precedence over AutoAUI/10BT).

When clear, 10BASE-T selected.

9 AutoAUI/10BT When set, automatic interface

selection enabled.

B

Mod

When set, the modified backoff

BackoffE algorithm is used. When clear,

the standard backoff algorithm is

used.

D

2-part When set, two-part deferral is

DefDis disabled.

Table 31. Physical Interface Configuration

Note that the CS8900A transmits in 10BASE-

T mode when no link pulses are being re-

ceived only if bit DisableLT is set in register

Test Control (Register 19).

5.6.2.2 Selecting which Events Cause Inter-

rupts

The TxCFG register (Register 7) and the

BufCFG register (Register B) are used to de-

termine which transmit events will cause inter-

rupts to the host processor. Tables 32 and 33

describe the interrupt enable (iE) bits in these

registers.

Register B, BufCFG

Bit Bit Name

Operation

8 Rdy4TxiE When set, there is an interrupt

whenever buffer space becomes

available for a transmit frame

(used with a Transmit Request).

9 TxUnder When set, there is an interrupt

runiE whenever the CS8900A runs out

of data after transmit has started.

C

TxCol When set, there is an interrupt

OvfloiE whenever the TxCol counter

overflows.

Table 33. Transmit Interrupt Configuration

Register 7, TxCFG

Bit Bit Name

Operation

6

Loss-of- When set, there is an interrupt

CRSiE whenever the CS8900A fails to

detect Carrier Sense after trans-

mitting the preamble (applies to

the AUI only).

7 SQErroriE When set, there is an interrupt

whenever there is an SQE error.

8

TxOKiE When set, there is an interrupt

whenever a frame is transmitted

successfully..

9

Out-of- When set, there is an interrupt

windowiE whenever a late collision is

detected.

A JabberiE When set, there is an interrupt

whenever there is a jabber condi-

tion.

B AnycolliE When set, there is an interrupt

whenever there is a collision.

F

16colliE When set, there is an interrupt

whenever the CS8900A attempts

to transmit a single frame 16

times.

Table 32. Transmitting Interrupt Configuration

5.6.3 Changing the Configuration

When the host configures these registers it

does not need to change them for subsequent

packet transmissions. If the host does choose

to change the TxCFG or BufCFG registers, it

may do so at any time. The effects of the

change are noticed immediately. That is, any

changes in the Interrupt Enable (iE) bits may

affect the packet currently being transmitted.

If the host chooses to change bits in the Li-

neCTL register after initialization, the Mod-

BackoffE bit and any receive related bit

(LoRxSquelch, SerRxON) may be changed at

any time. However, the Auto AUI/10BT and

AUIonly bits should not be changed while the

SerTxON bit is set. If any of these three bits

are to be changed, the host should first clear

the SerTxON bit (Register 13, LineCTL, Bit 7),

and then set it when the changes are com-

plete.

CIRRUS LOGIC PRODUCT DATASHEET

100

DS271F4

Share Link: