CS8900A-CQZ View Datasheet(PDF) - Cirrus Logic

Part Name

Description

Manufacturer

CS8900A-CQZ

Crystal LAN™ Ethernet Controller

Cirrus Logic 

CS8900A

Crystal LAN™ Ethernet Controller

be completely received. Usually, the DMA re-

ceive frame interrupt (RxDMAiE, bit 7, Regis-

ter B, BufCFG) is set so that the CS8900A

generates an interrupt when a frame is trans-

ferred by DMA. Figure 25 shows how a DMA

Receive Frame interrupt is processed.

In the interrupt service routine, the BufEvent

register (register C), bit RxDMA Frame (bit 7)

indicates that one or more receive frames

were transferred using DMA. The software

driver should maintain a pointer (e.g.

PDMA_START) that will point to the beginning

of a new frame. After the CS8900A is initial-

ized and before any frame is received, pointer

PDMA_START points to the beginning of the

DMA buffer memory area. The first read of the

DMA Frame Count, CDMA, commits the mem-

ory covered by the CDMA count, and the DMA

cannot overwrite this committed space until

the space is freed. The driver then processes

the frames described by the CDMA count and

makes a second read of the DMA frame count.

This second read frees the buffer memory

space described by the CDMA counter.

During the frame processing, the software

should advance the PDMA_START pointer. At

the end of processing a frame, pointer

PDMA_START should be made to align with a

double-word boundary. The software remains

in the loop until the DMA frame count read is

zero.

DMA Buffer

Base Address

"H oles" due to

d o u ble -w o rd

alignm ent

RxStatus - Fram e 1

RxLength - Frame 1

Frame 1

DM A Byte Count

(PacketPage base + 012Ah)

RxStatus - Fram e 2

RxLength - Frame 2

Frame 2

RxStatus - Fram e 3

RxLength - Frame 3

DMA Start of Fram e

register (PacketPage

base + 0126H)

points here.

Frame 3

Figure 24. Example of Frames Stored in DMA

CIRRUS LOGIC PRODUCT DATASHEET

DS271F4

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