CS8900A-CQZ View Datasheet(PDF) - Cirrus Logic

Part Name

Description

Manufacturer

CS8900A-CQZ

Crystal LAN™ Ethernet Controller

Cirrus Logic 

CS8900A

Crystal LAN™ Ethernet Controller

to and from the host. The host simply writes to

and reads from these locations and internal

buffer memory is dynamically allocated be-

tween transmit and receive as needed. This

provides more efficient use of buffer memory

and better overall network performance. As a

result of this dynamic allocation, only one re-

ceive frame (starting at PacketPage base +

0400h) and one transmit frame (starting at

PacketPage base + 0A00h) are directly acces-

sible. See Section 4.7 on page 72.

4.2 PacketPage Memory Map

Table 13 shows the CS8900A PacketPage

memory address map: s

PacketPage # of Type

Description

Address Bytes

Bus Interface Registers

0000h

4 Read-only Product Identification Code

0004h

28

-

Reserved

0020h

2 Read/Write I/O Base Address

0022h

2 Read/Write Interrupt Number (0,1,2,or 3)

0024h

2 Read/Write DMA Channel Number (0, 1, or 2)

0026h

2 Read-only DMA Start of Frame

0028h

2 Read-only DMA Frame Count (12 Bits)

002Ah

2 Read-only RxDMA Byte Count

002Ch

0030h

4 Read/Write Memory Base Address Register

(20 Bit)

4 Read/Write Boot PROM Base Address

0034h

4 Read/Write Boot PROM Address Mask

0038h

0040h

8

-

Reserved

2 Read/Write EEPROM Command

0042h

2 Read/Write EEPROM Data

0044h

0050h

12

-

Reserved

2 Read only Received Frame Byte Counter

0052h

174

-

Reserved

Status and Control Registers

Cross Reference

Section 4.3 on page 44

Note 2

Section 4.3 on page 44,

Section 4.7 on page 72

Section 3.2 on page 18,

Section 4.3 on page 44

Section 3.2 on page 18,

Section 4.3 on page 44

Section 4.3 on page 44,

Section 5.3 on page 90

Sections Section 4.3 on page 44,

”Receive DMA”

Section 4.3 on page 44,

Section 5.3 on page 90

Section 4.3 on page 44,

Section 4.9 on page 73

Section 3.6 on page 26,

Section 4.3 on page 44

Section 3.6 on page 26,

Section 4.3 on page 44

Note 2

Section 3.5 on page 25,

Section 4.3 on page 44

Section 3.5 on page 25,

Section 4.3 on page 44

Note 2

Section 4.3 on page 44,

Section 5.2.9 on page 86

Note 2

Notes: 1. All registers are accessed as words only.

2. Read operation from the reserved location provides undefined data. Writing to a reserved location or

undefined bits may result in unpredictable operation of the CS8900A.

Table 13. PacketPage Memory Address Map

CIRRUS LOGIC PRODUCT DATASHEET

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