D950CORE View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

D950CORE

16-Bit Fixed Point Digital Signal Processor (DSP) Core

STMicroelectronics 

D950-Core

DIEi:

Enable Interrupt

0: Interrupt request output associated to channel i is masked (def.)

1: Interrupt request output associated to channel i is not masked

DMS: Mask Sensitivity control register

Two bits are dedicated to each DMA channel (bits 0 and 1 to channel 0, bits 4 and 5 to channel

1, bits 8 and 9 to channel 2, bits 12 and 13 to channel 3). After reset, DMS default value is

0x3333.

15 14 13 12 11 10 9

87

-

- DSE3 DMK3 -

- DSE2 DMK2 -

65 43

- DSE1 DMK1 -

21

0

- DSE0 DMK0

DSEi:

DMKi:

DMA Sensitivity

0: Low level

1: Falling edge (def.)

DMA Mask

0: DMA channel not masked

1: DMA channel masked (def.)

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