FDC37C672 View Datasheet(PDF) - SMSC -> Microchip

Part Name

Description

Manufacturer

FDC37C672

Enhanced Super I/O Controller with Fast IR

SMSC -> Microchip 

NAME

WDT_VAL

Default = 0x00

on Vcc POR or

Reset_Drv

WDT_CFG

Default = 0x00

on Vcc POR or

Reset_Drv

WDT_CTRL

Default = 0x00

Cleared by VTR POR

Enhanced Super I/O Controller with Fast IR

Datasheet

REG INDEX

0xF2

DEFINITION

Watch-dog Timer Time-out Value

Binary coded, units = minutes(default) or seconds, selectable

via Bit[7] of Reg 0xF1, LD 8.

0x00 Time out disabled

0x01 Time-out = 1 minute (second)

STATE

C

0xFF Time-out = 255 minutes (seconds)

0xF3

Watch-dog timer Configuration

C

Bit[0] Joy-stick Enable

=1 WDT is reset upon an I/O read or write of the Game

Port

=0 WDT is not affected by I/O reads or writes to the Game

Port.

Bit[1] Keyboard Enable

=1 WDT is reset upon a Keyboard interrupt.

=0 WDT is not affected by Keyboard interrupts.

Bit[2] Mouse Enable

=1 WDT is reset upon a Mouse interrupt

=0 WDT is not affected by Mouse interrupts.

Bit[3] Reserved

Bits[7:4] WDT Interrupt Mapping

1111 = IRQ15

0011 = IRQ3

0010 = Invalid

0001 = IRQ1

0000 = Disable

0xF4

Watch-dog timer Control

C

Bit[0] Watch-dog Status Bit, R/W

=1 WD timeout occurred

=0 WD timer counting

Bit[1] Reserved

Bit[2] Force Timeout, W

=1 Forces WD timeout event; this bit is self-clearing

Bit[3] P20 Force Timeout Enable, R/W

= 1 Allows rising edge of P20, from the Keyboard

Controller, to force the WD timeout event. A WD

timeout event may still be forced by setting the Force

Timeout Bit, bit 2.

= 0 P20 activity does not generate the WD timeout event.

Note: The P20 signal will remain high for a minimum of 1us

and can remain high indefinitely. Therefore, when P20

forced timeouts are enabled, a self-clearing edge-

detect circuit is used to generate a signal which is

ORed with the signal generated by the Force Timeout

Bit.

Bit[7:4] Reserved. Set to 0

SMSC FDC37C672

Page 142

DATASHEET

Rev. 10-29-03

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