FDC37C672 View Datasheet(PDF) - SMSC -> Microchip
Part Name
Description
Manufacturer
FDC37C672 Datasheet PDF : 173 Pages
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Enhanced Super I/O Controller with Fast IR
Datasheet
Table 21.2 - EPP 1.9 Data or Address Cycle Timing Parameters
NAME
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
t14
t15
t16
t17
t18
t19
t20
t21
t22
DESCRIPTION
nIOW Asserted to PDATA Valid
nWAIT Asserted to nWRITE Change (Note 21.13)
nWRITE to Command Asserted
nWAIT Deasserted to Command Deasserted (Note 21.13)
nWAIT Asserted to PDATA Invalid (Note 21.13)
Time Out
Command Deasserted to nWAIT Asserted
SDATA Valid to nIOW Asserted
nIOW Deasserted to DATA Invalid
nIOW Asserted to IOCHRDY Asserted
nWAIT Deasserted to IOCHRDY Deasserted (Note 21.13)
IOCHRDY Deasserted to nIOW Deasserted
nIOW Asserted to nWRITE Asserted
nWAIT Asserted to Command Asserted (Note 21.13)
Command Asserted to nWAIT Deasserted
PDATA Valid to Command Asserted
Ax Valid to nIOW Asserted
nIOW Asserted to Ax Invalid
nIOW Deasserted to nIOW or nIOR Asserted
nWAIT Asserted to nWRITE Asserted (Note 21.13)
nWAIT Asserted to PDIR Low
PDIR Low to nWRITE Asserted
MIN
TYP MAX UNITS
0
50
ns
60
185
ns
5
35
ns
60
190
ns
0
ns
10
12
µs
0
ns
10
ns
0
ns
0
24
ns
60
160
ns
10
ns
0
70
ns
60
210
ns
0
10
µs
10
ns
40
ns
10
ns
40
ns
60
185
ns
0
ns
0
ns
Note 21.13 nWAIT must be filtered to compensate for ringing on the parallel bus cable. WAIT is considered to have
settled after it does not transition for a minimum of 50 nsec.
SMSC FDC37C672
Page 158
DATASHEET
Rev. 10-29-03
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