FDC37C672 View Datasheet(PDF) - SMSC -> Microchip
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Description
Manufacturer
FDC37C672 Datasheet PDF : 173 Pages
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Enhanced Super I/O Controller with Fast IR
Datasheet
Table 21.3 - EPP 1.9 Data or Address Read Cycle Timing Parameters
NAME
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
t14
t15
t16
t17
t18
t19
t20
t21
t22
t23
t24
t25
t26
t27
t28
DESCRIPTION
PDATA Hi-Z to Command Asserted
nIOR Asserted to PDATA Hi-Z
nWAIT Deasserted to Command Deasserted (Note 21.14)
Command Deasserted to PDATA Hi-Z
Command Asserted to PDATA Valid
PDATA Hi-Z to nWAIT Deasserted
PDATA Valid to nWAIT Deasserted
nIOR Asserted to IOCHRDY Asserted
nWRITE Deasserted to nIOR Asserted (Note 21.15)
nWAIT Deasserted to IOCHRDY Deasserted (Note 21.14)
IOCHRDY Deasserted to nIOR Deasserted
nIOR Deasserted to SDATA Hi-Z (Hold Time)
PDATA Valid to SDATA Valid
nWAIT Asserted to Command Asserted
Time Out
nWAIT Deasserted to PDATA Driven (Note 21.14)
nWAIT Deasserted to nWRITE Modified (Note 21.14, Note
21.15)
SDATA Valid to IOCHRDY Deasserted (Note 21.16)
Ax Valid to nIOR Asserted
nIOR Deasserted to Ax Invalid
nWAIT Asserted to nWRITE Deasserted
nIOR Deasserted to nIOW or nIOR Asserted
nWAIT Asserted to PDIR Set (Note 21.14)
PDATA Hi-Z to PDIR Set
nWAIT Asserted to PDATA Hi-Z (Note 21.14)
PDIR Set to Command
nWAIT Deasserted to PDIR Low (Note 21.14)
nWRITE Deasserted to Command
MIN
TYP MAX
0
30
0
50
60
180
0
0
0
0
0
24
0
60
160
0
0
40
0
75
0
195
10
12
60
190
60
190
0
85
40
10
10
0
185
40
60
185
0
60
180
0
20
60
180
1
Note 21.14 nWAIT is considered to have settled after it does not transition for a minimum of 50 ns.
Note 21.15 When not executing a write cycle, EPP nWRITE is inactive high.
Note 21.16 85 is true only if t7 = 0.
UNITS
ns
ns
ns
ns
ns
µs
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SMSC FDC37C672
Page 160
DATASHEET
Rev. 10-29-03
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