FDC37C672 View Datasheet(PDF) - SMSC -> Microchip
Part Name
Description
Manufacturer
FDC37C672 Datasheet PDF : 173 Pages
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Enhanced Super I/O Controller with Fast IR
Datasheet
Table 21.4 - EPP 1.7 Data or Address Write Cycle Parameters
NAME
t1
t2
t3
t4
t5
t6
t8
t9
t10
t11
t12
t13
t16
t17
t18
t19
t20
t21
DESCRIPTION
nIOW Asserted to PDATA Valid
Command Deasserted to nWRITE Change
nWRITE to Command
nIOW Deasserted to Command Deasserted (Note 21.18)
Command Deasserted to PDATA Invalid
Time Out
SDATA Valid to nIOW Asserted
nIOW Deasserted to DATA Invalid
nIOW Asserted to IOCHRDY Asserted
nWAIT Deasserted to IOCHRDY Deasserted
IOCHRDY Deasserted to nIOW Deasserted
nIOW Asserted to nWRITE Asserted
PDATA Valid to Command Asserted
Ax Valid to nIOW Asserted
nIOW Deasserted to Ax Invalid
nIOW Deasserted to nIOW or nIOR Asserted
nWAIT Asserted to IOCHRDY Deasserted
Command Deasserted to nWAIT Deasserted
MIN
TYP MAX UNITS
0
50
ns
0
40
ns
5
35
ns
50
ns
50
ns
10
12
µs
10
ns
0
ns
0
24
ns
40
ns
10
ns
0
50
ns
10
35
ns
40
ns
10
µs
100
ns
45
ns
0
ns
Note 21.17 nWRITE is controlled by clearing the PDIR bit to "0" in the control register before performing an EPP
Write.
Note 21.18 The number is only valid if nWAIT is active when IOW goes active.
SMSC FDC37C672
Page 162
DATASHEET
Rev. 10-29-03
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