FDC37C672 View Datasheet(PDF) - SMSC -> Microchip
Part Name
Description
Manufacturer
FDC37C672 Datasheet PDF : 173 Pages
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Enhanced Super I/O Controller with Fast IR
Datasheet
A0-A10
t19
nIOR
SD<7:0>
IOCHRDY
nWRITE
PD<7:0>
nDATASTB
nADDRSTB
nWAIT
PDIR
t8
t3
t23
t15
t13
t20
t11
t22
t12
t10
t5
t4
t2
t21
Figure 21.16 - EPP 1.7 Data or Address Read Cycle
Table 21.5 - EPP 1.7 Data or Address Read Cycle Parameters
NAME
t2
t3
t4
t5
t8
t10
t11
t12
t13
t15
t19
t20
t21
t22
t23
DESCRIPTION
nIOR Deasserted to Command Deasserted
nWAIT Asserted to IOCHRDY Deasserted
Command Deasserted to PDATA Hi-Z
Command Asserted to PDATA Valid
nIOR Asserted to IOCHRDY Asserted
nWAIT Deasserted to IOCHRDY Deasserted
IOCHRDY Deasserted to nIOR Deasserted
nIOR Deasserted to SDATA High-Z (Hold Time)
PDATA Valid to SDATA Valid
Time Out
Ax Valid to nIOR Asserted
nIOR Deasserted to Ax Invalid
Command Deasserted to nWAIT Deasserted
nIOR Deasserted to nIOW or nIOR Asserted
nIOR Asserted to Command Asserted
MIN
TYP MAX UNITS
50
ns
0
40
ns
0
ns
0
ns
24
ns
50
ns
0
ns
0
40
ns
40
ns
10
12
µs
40
ns
10
ns
0
ns
40
ns
55
ns
Note: WRITE is controlled by setting the PDIR bit to "1" in the control register before performing an EPP Read.
SMSC FDC37C672
Page 163
DATASHEET
Rev. 10-29-03
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