FDC37C672 View Datasheet(PDF) - SMSC -> Microchip
Part Name
Description
Manufacturer
FDC37C672 Datasheet PDF : 173 Pages
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Enhanced Super I/O Controller with Fast IR
Datasheet
6.1.8 Digital Input Register (DIR)
Address 3F7 READ ONLY
This register is read-only in all modes.
PC-AT Mode
7
6
5
4
3
2
1
0
DSK
CHG
RESET N/A N/A N/A N/A N/A N/A N/A N/A
COND.
BIT 0 - 6 UNDEFINED
The data bus outputs D0 - 6 will remain in a high impedance state during a read of this register.
BIT 7 DSKCHG
This bit monitors the pin of the same name and reflects the opposite value seen on the disk cable or the
value programmed in the Force Disk Change Register (see Configuration Register LD8:CRC1[1:0]).
PS/2 Mode
7
6
5
4
3
2
1
0
DSK
1
1
1
1 DRATE DRATE nHIGH
CHG
SEL1 SEL0 nDENS
RESET N/A N/A N/A N/A N/A N/A N/A
1
COND.
BIT 0 nHIGH DENS
This bit is low whenever the 500 Kbps or 1 Mbps data rates are selected, and high when 250 Kbps and
300 Kbps are selected.
BITS 1 - 2 DATA RATE SELECT
These bits control the data rate of the floppy controller. See Table 6.10 for the settings corresponding to
the individual data rates. The data rate select bits are unaffected by a software reset, and are set to 250
Kbps after a hardware reset.
BITS 3 - 6 UNDEFINED
Always read as a logic "1"
BIT 7 DSKCHG
This bit monitors the pin of the same name and reflects the opposite value seen on the disk cable or the
value programmed in the Force Disk Change Register (see Configuration Register LD8:CRC1[1:0]).
SMSC FDC37C672
Page 31
PRELIMINARY DATASHEET
Rev. 10-29-03
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