FDC37C672 View Datasheet(PDF) - SMSC -> Microchip

Part Name

Description

Manufacturer

FDC37C672

Enhanced Super I/O Controller with Fast IR

SMSC -> Microchip 

6.2

Enhanced Super I/O Controller with Fast IR

Datasheet

RESET

There are three sources of system reset on the FDC: the RESET pin of the FDC, a reset generated via a

bit in the DOR, and a reset generated via a bit in the DSR. At power on, a Power On Reset initializes the

FDC. All resets take the FDC out of the power down state.

All operations are terminated upon a RESET, and the FDC enters an idle state. A reset while a disk write

is in progress will corrupt the data and CRC.

On exiting the reset state, various internal registers are cleared, including the Configure command

information, and the FDC waits for a new command. Drive polling will start unless disabled by a new

Configure command.

6.2.1 RESET Pin (Hardware Reset)

The RESET pin is a global reset and clears all registers except those programmed by the Specify

command. The DOR reset bit is enabled and must be cleared by the host to exit the reset state.

6.2.2 DOR Reset vs. DSR Reset (Software Reset)

These two resets are functionally the same. Both will reset the FDC core, which affects drive status

information and the FIFO circuits. The DSR reset clears itself automatically while the DOR reset requires

the host to manually clear it. DOR reset has precedence over the DSR reset. The DOR reset is set

automatically upon a pin reset. The user must manually clear this reset bit in the DOR to exit the reset

state.

6.3

Modes of Operation

The FDC has three modes of operation, PC/AT mode, PS/2 mode and Model 30 mode. These are

determined by the state of the IDENT and MFM bits 6 and 5 respectively of CRxx.

6.3.1 PC/AT mode - (IDENT high, MFM a "don't care")

The PC/AT register set is enabled, the DMA enable bit of the DOR becomes valid (FINTR and DRQ can

be hi Z), and TC and DENSEL become active high signals.

6.3.2 PS/2 mode - (IDENT low, MFM high)

This mode supports the PS/2 models 50/60/80 configuration and register set. The DMA bit of the DOR

becomes a "don't care", (FINTR and DRQ are always valid), TC and DENSEL become active low.

6.3.3 Model 30 mode - (IDENT low, MFM low)

This mode supports PS/2 Model 30 configuration and register set. The DMA enable bit of the DOR

becomes valid (FINTR and DRQ can be hi Z), TC is active high and DENSEL is active low.

SMSC FDC37C672

Page 36

DATASHEET

Rev. 10-29-03

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