FDC37B72X(1999) View Datasheet(PDF) - SMSC -> Microchip

Part Name

Description

Manufacturer

FDC37B72X
(Rev.:1999)

128 Pin Enhanced Super I/O Controller with ACPI Support

SMSC -> Microchip 

RESET

There are three sources of system reset on the

FDC: the RESET pin of the FDC, a reset

generated via a bit in the DOR, and a reset

generated via a bit in the DSR. At power on, a

Power On Reset initializes the FDC. All resets

take the FDC out of the power down state.

All operations are terminated upon a RESET,

and the FDC enters an idle state. A reset while

a disk write is in progress will corrupt the data

and CRC.

On exiting the reset state, various internal

registers are cleared, including the Configure

command information, and the FDC waits for a

new command. Drive polling will start unless

disabled by a new Configure command.

RESET Pin (Hardware Reset)

The RESET pin is a global reset and clears all

registers except those programmed by the

Specify command. The DOR reset bit is

enabled and must be cleared by the host to exit

the reset state.

DOR Reset vs. DSR Reset (Software Reset)

These two resets are functionally the same.

Both will reset the FDC core, which affects drive

status information and the FIFO circuits. The

DSR reset clears itself automatically while the

DOR reset requires the host to manually clear it.

DOR reset has precedence over the DSR reset.

The DOR reset is set automatically upon a pin

reset. The user must manually clear this reset

bit in the DOR to exit the reset state.

MODES OF OPERATION

The FDC has three modes of operation, PC/AT

mode, PS/2 mode and Model 30 mode. These

are determined by the state of the IDENT and

MFM bits 3 and 2 respectively of LD8CRF0.

PC/AT mode - (IDENT high, MFM a "don't

care")

The PC/AT register set is enabled, the DMA

enable bit of the DOR becomes valid (FINTR

and DRQ can be hi Z), and TC and DENSEL

become active high signals.

PS/2 mode - (IDENT low, MFM high)

This mode supports the PS/2 models 50/60/80

configuration and register set. The DMA bit of

the DOR becomes a "don't care", (FINTR and

DRQ are always valid), TC and DENSEL

become active low.

Model 30 mode - (IDENT low, MFM low)

This mode supports PS/2 Model 30

configuration and register set. The DMA enable

bit of the DOR becomes valid (FINTR and DRQ

can be hi Z), TC is active high and DENSEL is

active low.

DMA TRANSFERS

DMA transfers are enabled with the Specify

command and are initiated by the FDC by

activating the FDRQ pin during a data transfer

command. The FIFO is enabled directly by

asserting nDACK and addresses need not be

valid.

Note that if the DMA controller (i.e. 8237A) is

programmed to function in verify mode, a

pseudo read is performed by the FDC based

only on nDACK. This mode is only available

when the FDC has been configured into byte

mode (FIFO disabled) and is programmed to do

a read. With the FIFO enabled, the FDC can

perform the above operation by using the new

Verify command; no DMA operation is needed.

Two DMA transfer modes are supported for the

FDC: Single Transfer and Burst Transfer. In the

case of the single transfer, the DMA Req goes

active at the start of the DMA cycle, and the

DMA Req is deasserted after the nDACK. In the

case of the burst transfer, the Req is held active

34

Share Link: