FDC37B72X(1999) View Datasheet(PDF) - SMSC -> Microchip

Part Name

Description

Manufacturer

FDC37B72X
(Rev.:1999)

128 Pin Enhanced Super I/O Controller with ACPI Support

SMSC -> Microchip 

SYMBOL

PRETRK

R

RCN

SC

SK

SRT

ST0

ST1

ST2

ST3

WGATE

NAME

DESCRIPTION

Precompensation Programmable from track 00 to FFH.

Start Track

Number

Sector Address The sector number to be read or written. In multi-sector transfers,

this parameter specifies the sector number of the first sector to be

read or written.

Relative Cylinder Relative cylinder offset from present cylinder as used by the

Number

Relative Seek command.

Number of

The number of sectors per track to be initialized by the Format

Sectors Per Track command. The number of sectors per track to be verified during a

Verify command when EC is set.

Skip Flag

When set to 1, sectors containing a deleted data address mark will

automatically be skipped during the execution of Read Data. If

Read Deleted is executed, only sectors with a deleted address

mark will be accessed. When set to "0", the sector is read or

written the same as the read and write commands.

Step Rate Interval The time interval between step pulses issued by the FDC.

Programmable from 0.5 to 8 milliseconds in increments of 0.5 ms

at the 1 Mbit data rate. Refer to the SPECIFY command for actual

delays.

Status 0

Registers within the FDC which store status information after a

Status 1

command has been executed. This status information is available

Status 2

to the host during the result phase after command execution.

Status 3

Write Gate

Alters timing of WE to allow for pre-erase loads in perpendicular

drives.

40

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