LX64C-5FN100C View Datasheet(PDF) - Lattice Semiconductor
Part Name
Description
Manufacturer
LX64C-5FN100C Datasheet PDF : 72 Pages
| |||
Lattice Semiconductor
ispGDX2 Family Data Sheet
LOCKIN Time
Symbol
tSCLOCK
Description
CSPLL Lock Time
tCDRLOCK
CDRPLL Lock-in Time
tSYNC
SyncPat Length
tCAL
CAL Duration
tSUSYNC
SyncPat Set-up Time to CAL
tHDSYNC
SyncPat Hold Time from CAL
1. REFCLK clock period.
Mode
All
SS
10B12B
8B10B
SS
SS
SS
SS
Condition
After input is stabilized
With SS mode sync pattern
With 10B12B sync pattern
With 8B10B idle pattern
Min.
1200
1100
50
50
Max.
25
1024
1024
960
Units
μS
tRCP1
tRCP
tRCP
tRCP
tRCP
tRCP
tRCP
REFCLK and SS_CLKIN Timing
Symbol
tDREFCLK
tJPPREFCLK
tPWREFCLK
tRFREFCLK
Description
Frequency Deviation Between TX REFCLK and
CDRX REFCLK on One Link
REFCLK, SS_CLKIN Peak-to-Peak Period Jitter
REFCLK, SS_CLKIN Pulse Width, (80% to 80% or
20% to 20%).
REFCLK, SS_CLKIN Rise/Fall Time (20% to 80% or
80% to 20%)
Mode
8B10B/
10B12B
All
All
All
Condition
Random Jitter
Min.
-100
1
Max.
100
0.01
Units
ppm
UIPP
ns
2
ns
Serializer Timing2
Symbol
Description
Mode
Condition
Min.
Max.
Units
tJPPSOUT
tJPP8B10B
SOUT Peak-to-Peak Output Data Jitter
SOUT Peak-to-Peak Random Jitter
SOUT Peak-to-Peak Deterministic Jitter
All
8B10B
8B10B
fCLK with no jitter
800 Mbps w/K28.7-
800 Mbps w/K28.5+
0.25
UIPP
130
ps
160
ps
tRFSOUT
SOUT Output Data Rise/Fall Time (20%, LVDS
80%)
BLVDS
700
ps
900
ps
tCOSOUT
REFCLK to SOUT Delay
SS/8B10B
10B12B
2Bt1 + 2 2Bt1 +10
ns
1Bt1 + 2 1Bt1 +10
ns
tSKTX
Skew of SOUT with Respect to
SS_CLKOUT
SS
250
ps
tCKOSOUT
SS_CLKOUT to bit0 of SOUT
SS
2Bt1 - tSKTX 2Bt1 + tSKTX ns
tHSITXDDATAS TXD Data Setup Time
All Note 3
1.5
ns
tHSITXDDATAH TXD Data Hold Time
All Note 3
1.0
ns
1. Bt: Bit Time Period. High Speed Serial Bit Time.
2. The SIN and SOUT jitter specifications listed above are under the condition that the clock tree that drives the REFCLK to sysHSI Block is in
sysCLOCK PLL BYPASS mode.
3. Internal timing for reference only.
40
Share Link: 