LX64C-5FN100C View Datasheet(PDF) - Lattice Semiconductor
Part Name
Description
Manufacturer
LX64C-5FN100C Datasheet PDF : 72 Pages
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Lattice Semiconductor
ispGDX2 Family Data Sheet
Deserializer Timing
Symbol
Description
fDSIN
SIN Frequency Deviation from REFCLK
eoSIN
ber
SIN Eye Opening Tolerance
Bit Error Rate
tHSIOUTVALIDPRE
RXD, SYDT Valid Time Before RECCLK Fall-
ing Edge
tHSIOUTVALIDPOST
RXD, SYDT Valid Time
After RECCLK Falling Edge
tDSIN
Bit 0 of SIN Delay to RXD Valid at RECCLK
Falling edge
1. Eye opening based on jitter frequency of 100KHz.
2. Lower frequency operation assumes maximum eye closure of 800ps.
3. Internal timing for reference only.
Mode
8B10B/
10B12B
All
All
All
All
All
Conditions
Notes 1, 2
Min.
-100
0.45
Note 3 tRCP/2 - 0.7
Max.
100
10-12
Units
ppm
UIPP
Bits
ns
Note 3 tRCP/2 - 0.7
ns
1.5 tRCP + 1.5 tRCP +
4.5Bt + 2 4.5Bt + 10
ns
Lock-in Timing
CDRX_SS LOCK-IN (DE-SKEW) TIMING
SIN
MIN. 1200 SYNCPAT
CAL
MIN. 1100 LS CYCLE
SYDT
tSUSYNC
RXD(0:7)
SYNCPAT
TRAINING SEQUENCE
DATA (SERIAL)
tHDSYNC
DATA (PARALLEL)
SS MODE DATA TRANSFER
CDR_10B12B LOCK-IN TIMING
SIN
1024 SYNCPAT
SYDT
RXD(0:9)
SYNCPAT
DATA (SERIAL)
DATA (PARALLEL)
41
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